From 7570a035cf061e8d628c2a96507df20ff65449be Mon Sep 17 00:00:00 2001
From: Manish Pandey <mapa@qti.qualcomm.com>
Date: Thu, 3 Nov 2022 22:02:56 +0530
Subject: [PATCH] ARM: dts: msm: Modified UFS device ref_clk in Anorak HMT
 platform

Modified UFS device ref_clk to RPMH_LN_BB_CLK8 clock for
Anorak IDP Topanga Hamilton(HMT) platform to improve IPN phase noise.

Change-Id: I5ef525c1888bf2a00858a4482e33d8f922825765
---
 qcom/anorak-idp-top-hmt.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/qcom/anorak-idp-top-hmt.dtsi b/qcom/anorak-idp-top-hmt.dtsi
index ca273aee..1b0f26bc 100644
--- a/qcom/anorak-idp-top-hmt.dtsi
+++ b/qcom/anorak-idp-top-hmt.dtsi
@@ -1 +1,27 @@
 #include "anorak-idp-hmt.dtsi"
+#include <dt-bindings/clock/qcom,gcc-anorak.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+&ufshc_mem {
+	clock-names =
+		"core_clk",
+		"bus_aggr_clk",
+		"iface_clk",
+		"core_clk_unipro",
+		"core_clk_ice",
+		"ref_clk",
+		"tx_lane0_sync_clk",
+		"rx_lane0_sync_clk",
+		"rx_lane1_sync_clk";
+	clocks =
+		<&gcc GCC_UFS_PHY_AXI_CLK>,
+		<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+		<&gcc GCC_UFS_PHY_AHB_CLK>,
+		<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+		<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+		<&rpmhcc RPMH_LN_BB_CLK8>,
+		<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+		<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+		<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+};
+