From e711391f834bcb8902c5172f79e1ef31236395c2 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 10 Jul 2020 16:31:07 -0700 Subject: [PATCH 1/5] ARM: dts: msm: Add initial smmu dt for sdxlemur Add the apps smmu device. Change-Id: I12dad92706fda1d086003f4c26b5f868d317dc79 --- qcom/msm-arm-smmu-sdxlemur.dtsi | 89 +++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 1 + 2 files changed, 90 insertions(+) create mode 100644 qcom/msm-arm-smmu-sdxlemur.dtsi diff --git a/qcom/msm-arm-smmu-sdxlemur.dtsi b/qcom/msm-arm-smmu-sdxlemur.dtsi new file mode 100644 index 00000000..47e46d63 --- /dev/null +++ b/qcom/msm-arm-smmu-sdxlemur.dtsi @@ -0,0 +1,89 @@ +#include + +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x40000>, + <0x15042000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interconnects = <&system_noc MASTER_APPSS_PROC + &mem_noc SLAVE_IMEM_CFG>; + qcom,active-only; + + periph_tbu: periph_tbu@15045000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15045000 0x1000>, + <0x15042200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interconnects = <&system_noc MASTER_APPSS_PROC + &mem_noc SLAVE_IMEM_CFG>; + qcom,active-only; + }; + + ipa_tbu: ipa_tbu@15049000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15049000 0x1000>, + <0x15042208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + interconnects = <&system_noc MASTER_APPSS_PROC + &mem_noc SLAVE_IMEM_CFG>; + qcom,active-only; + }; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x100 0>; + qcom,iommu-dma = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x101 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d153b49f..b4b9924c 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -469,4 +469,5 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-stub-regulator.dtsi" +#include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-usb.dtsi" From a5291796926e3d23d156c8d0eaca59f78220ed84 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 10 Jul 2020 16:31:16 -0700 Subject: [PATCH 2/5] ARM: dts: msm: Add memory map for sdxlemur Update the memory map to version 1.0 Change-Id: I39c9485e78acebb7b9fd759e9cfca04ec5df57e2 --- qcom/sdxlemur.dtsi | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index b4b9924c..8225bc20 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -20,15 +20,19 @@ memory { device_type = "memory"; reg = <0 0>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; - peripheral2_mem: peripheral2_region@8fd00000 { + mpss_adsp_mem: mpss_adsp_region@90800000 { no-map; - reg = <0x8fd00000 0x140000>; - label = "peripheral2_mem"; + reg = <0x90800000 0x10000000>; + }; + + tz_mem: tz_mem_region@8ff00000 { + no-map; + reg = <0x8ff00000 0x600000>; }; smem_mem: smem_region@8fe40000 { @@ -36,6 +40,26 @@ reg = <0x8fe40000 0xc0000>; label = "smem_mem"; }; + + peripheral_mem: peripheral_region@8fd00000 { + no-map; + reg = <0x8fd00000 0x140000>; + }; + + /* + * The exact size of this region may vary based on DDR size. + * 0x100000 will be valid for all DDR sizes at the cost of + * slightly reducing the memory available for HLOS. + */ + peripheral_mem2: peripheral_region2@8fb00000 { + no-map; + reg = <0x8fb00000 0x100000>; + }; + + mpss_dsm: mpss_dsm_region@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; }; cpus { From 642330bb8ad441949274f9b679018a236fbbd1b3 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Tue, 14 Jul 2020 15:55:39 -0700 Subject: [PATCH 3/5] ARM: dts: msm: Add CMA region for sdxlemur Add a 12MB CMA region. Change-Id: Iba50fd5f19d91bf46297d72695211170054ccae3 --- qcom/sdxlemur.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 8225bc20..019bc951 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -60,6 +60,16 @@ no-map; reg = <0x8c400000 0x3200000>; }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x00000000 0xffffffff>; + reusable; + alignment = <0x400000>; + size = <0xC00000>; + linux,cma-default; + }; }; cpus { From 92e755017eb87ae41252dab9a5a8f1feccad8967 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 10 Jul 2020 16:31:20 -0700 Subject: [PATCH 4/5] ARM: dts: msm: Add ion device for sdxlemur Describe the available ion heaps. Change-Id: I300b6432ccd44517a6f76e08f684cc076e82c8c1 --- qcom/sdxlemur-ion.dtsi | 15 +++++++++++++++ qcom/sdxlemur.dtsi | 1 + 2 files changed, 16 insertions(+) create mode 100644 qcom/sdxlemur-ion.dtsi diff --git a/qcom/sdxlemur-ion.dtsi b/qcom/sdxlemur-ion.dtsi new file mode 100644 index 00000000..5eb8ae2d --- /dev/null +++ b/qcom/sdxlemur-ion.dtsi @@ -0,0 +1,15 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + }; +}; + diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 019bc951..d05bd4f1 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -504,4 +504,5 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-stub-regulator.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" +#include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" From ad214af3c7ab0e823f36f93342cdaa3def040d9e Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Fri, 10 Jul 2020 16:31:24 -0700 Subject: [PATCH 5/5] dt-bindings: Document child nodes for iommu-debug-test devices The child nodes describe a test configuration. Change-Id: I04b829f6a8f2a1495a0156c37fc29ba961238ed1 --- bindings/iommu/iommu-debug-test.yaml | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/bindings/iommu/iommu-debug-test.yaml b/bindings/iommu/iommu-debug-test.yaml index eda386db..baa03518 100644 --- a/bindings/iommu/iommu-debug-test.yaml +++ b/bindings/iommu/iommu-debug-test.yaml @@ -18,14 +18,16 @@ properties: items: - const: iommu-debug-test - iommus: - minItems: 1 - items: - - description: IOMMU specifier with a SID and an SMR mask - description: - The SID in the IOMMU specifier is a placeholder so that the SMMU driver - can recognize the node. Our test uses ATOS, which doesn't use SIDs anyway, - so using a dummy value is ok. + child nodes: + compatible: : iommu-debug-usecase + iommus: + minItems: 1 + items: + - description: IOMMU specifier with a SID and an SMR mask + description: + The SID in the IOMMU specifier is a placeholder so that the SMMU driver + can recognize the node. Our test uses ATOS, which doesn't use SIDs anyway, + so using a dummy value is ok. required: - compatible @@ -35,5 +37,8 @@ examples: - | iommu_test_device { compatible = "iommu-debug-test"; - iommus = <&cpp_fd_smmu 42>; + basic_usecase { + compatible = "iommu-debug-usecase"; + iommus = <&cpp_fd_smmu 42>; + } };