From 7a4ab80643cbd6bd409eea058dad27a0eabf9873 Mon Sep 17 00:00:00 2001
From: Naman Padhiar <npadhiar@qti.qualcomm.com>
Date: Wed, 1 Dec 2021 19:21:18 +0530
Subject: [PATCH] ARM: dts: msm: Add CNSS2 node for cape + Kiwi

Add CNSS2 device tree entry for WLAN KIWI device parameters.

Change-Id: Ic2464917d2017e0d26e04745c7398610c5f108cd
---
 qcom/cape-kiwi.dtsi    | 140 ++++++++++++++++++++++++++++++++++++++++-
 qcom/cape-pinctrl.dtsi |   2 +-
 2 files changed, 140 insertions(+), 2 deletions(-)

diff --git a/qcom/cape-kiwi.dtsi b/qcom/cape-kiwi.dtsi
index b4726b01..1195dda4 100644
--- a/qcom/cape-kiwi.dtsi
+++ b/qcom/cape-kiwi.dtsi
@@ -1 +1,139 @@
-&soc { };
+#include <dt-bindings/interconnect/qcom,waipio.h>
+
+&wlan {
+	status = "disabled";
+};
+
+&cnss_pins {
+	cnss_host_sol_default: cnss_host_sol_default {
+		mux {
+			pins = "gpio48";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio48";
+			drive-strength = <4>;
+			bias-pull-down;
+		};
+	};
+
+	cnss_dev_sol_default: cnss_dev_sol_default {
+		mux {
+			pins = "gpio50";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio50";
+			drive-strength = <4>;
+			bias-pull-down;
+		};
+	};
+};
+
+&soc {
+	wlan_wcn7850: qcom,cnss-wcn7850@b0000000 {
+		compatible = "qcom,cnss-wcn7850";
+		reg = <0xb0000000 0x10000>;
+		reg-names = "smmu_iova_ipa";
+		wlan-en-gpio = <&tlmm 80 0>;
+		wlan-host-sol-gpio = <&tlmm 48 0>;
+		wlan-dev-sol-gpio = <&tlmm 50 0>;
+		pinctrl-names = "wlan_en_active", "wlan_en_sleep",
+				"sol_default";
+		pinctrl-0 = <&cnss_wlan_en_active>;
+		pinctrl-1 = <&cnss_wlan_en_sleep>;
+		pinctrl-2 = <&cnss_host_sol_default &cnss_dev_sol_default>;
+		qcom,wlan;
+		qcom,wlan-rc-num = <1>;
+		qcom,wlan-ramdump-dynamic = <0x780000>;
+		use-pm-domain;
+		qcom,same-dt-multi-dev;
+		mboxes = <&qmp_aop 0>;
+
+		vdd-wlan-io-supply = <&S10B>;
+		qcom,vdd-wlan-io-config = <1800000 1800000 0 0 0>;
+		vdd-wlan-supply = <&S3E>;
+		qcom,vdd-wlan-config = <1000000 1000000 0 0 0>;
+		vdd-wlan-aon-supply = <&S2E>;
+		qcom,vdd-wlan-aon-config = <980000 1040000 0 0 0>;
+		vdd-wlan-dig-supply = <&S11B>;
+		qcom,vdd-wlan-dig-config = <950000 1170000 0 0 0>;
+		vdd-wlan-rfa1-supply = <&S1C>;
+		qcom,vdd-wlan-rfa1-config = <1900000 2024000 0 0 0>;
+		vdd-wlan-rfa2-supply = <&S12B>;
+		qcom,vdd-wlan-rfa2-config = <1350000 2040000 0 0 0>;
+
+		interconnects =
+		<&pcie_noc MASTER_PCIE_1 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
+		<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
+
+		qcom,icc-path-count = <2>;
+		qcom,bus-bw-cfg-count = <9>;
+		qcom,bus-bw-cfg =
+		/** ICC Path 1 **/
+		<0 0>, /* no vote */
+		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<2250 1600000>,
+		/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<7500 1600000>,
+		/* medium: 60-240 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<30000 1600000>,
+		/* high: 240-1080 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
+		<100000 6448000>,
+		/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 1555 MHz */
+		<175000 6448000>,
+		/* ultra high: DBS mode snoc/anoc: 403 Mhz ddr: 2092 MHz */
+		<175000 6448000>,
+		/* super high: DBS mode snoc/anoc: 533 Mhz ddr: 3.2GHz */
+		<175000 8528000>,
+		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
+		 * ddr: 547.2 MHz
+		 */
+		<7500 3200000>,
+
+		/** ICC Path 2 **/
+		<0 0>,
+		/* ddr: 451.2 MHz */
+		<2250 1804800>,
+		/* ddr: 451.2 MHz */
+		<7500 1804800>,
+		/* ddr: 451.2 MHz */
+		<30000 1804800>,
+		/* ddr: 451.2 MHz */
+		<100000 1804800>,
+		/* ddr: 1555 MHz */
+		<175000 6220800>,
+		/* ddr: 2092 MHz */
+		<175000 8368000>,
+		/* ddr: 3.2 GHz */
+		<175000 12800000>,
+		/* ddr: 547.2 MHz */
+		<7500 2188800>;
+	};
+};
+
+&pcie1_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	cnss_pci1: cnss_pci1 {
+		reg = <0 0 0 0 0>;
+		qcom,iommu-group = <&cnss_pci_iommu_group1>;
+		memory-region = <&cnss_wlan_mem>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cnss_pci_iommu_group1: cnss_pci_iommu_group1 {
+			qcom,iommu-msi-size = <0x1000>;
+			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-pagetable = "coherent";
+			qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+					    "non-fatal";
+		};
+	};
+};
diff --git a/qcom/cape-pinctrl.dtsi b/qcom/cape-pinctrl.dtsi
index 4b9e7c52..67cf2cd0 100644
--- a/qcom/cape-pinctrl.dtsi
+++ b/qcom/cape-pinctrl.dtsi
@@ -2607,7 +2607,7 @@
 		};
 	};
 
-	cnss_pins {
+	cnss_pins: cnss_pins {
 		cnss_wlan_en_active: cnss_wlan_en_active {
 			mux {
 				pins = "gpio80";