From 7c912a6412ae6e8c5faafa67336ce4f722fea434 Mon Sep 17 00:00:00 2001 From: Pratyush Brahma Date: Wed, 13 Jul 2022 17:09:32 +0530 Subject: [PATCH] ARM: dts: msm: Add anorak smmu regulator and icc votes Add regulator and icc votes for TBUs in anorak smmu. Change-Id: I6e20f73deaefffebe135ca002562373966b06c2f --- qcom/msm-arm-smmu-anorak.dtsi | 67 +++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/qcom/msm-arm-smmu-anorak.dtsi b/qcom/msm-arm-smmu-anorak.dtsi index d99b700f..14c45225 100644 --- a/qcom/msm-arm-smmu-anorak.dtsi +++ b/qcom/msm-arm-smmu-anorak.dtsi @@ -204,6 +204,11 @@ /* For compute +15 deep PF */ <0x961 0x27 0x303>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_TCU>; + + qcom,active-only; + anoc_1_tbu: anoc_1_tbu@151c9000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x151c9000 0x1000>, @@ -211,6 +216,9 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; qcom,micro-idle; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_IMEM_CFG>; + qcom,active-only; qcom,iova-width = <36>; }; @@ -221,6 +229,9 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; qcom,micro-idle; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_IMEM_CFG>; + qcom,active-only; qcom,iova-width = <36>; }; @@ -231,6 +242,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -241,6 +257,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0xc00 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -251,6 +272,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1000 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + interconnects = <&mmss_noc MASTER_MDP0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -261,6 +287,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1400 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + interconnects = <&mmss_noc MASTER_MDP1 + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -271,6 +302,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc>; + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -281,6 +317,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc>; + interconnects = <&mmss_noc MASTER_MDP_CORE1_1 + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -291,6 +332,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2000 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + interconnects = <&nsp_noc MASTER_CDSP_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -301,6 +347,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2400 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu1_gdsc>; + interconnects = <&nsp_noc MASTER_CDSP_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -311,6 +362,9 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2800 0x400>; qcom,micro-idle; + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -321,6 +375,9 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x2c00 0x400>; qcom,micro-idle; + interconnects = <&pcie_noc MASTER_PCIE_0 + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <36>; }; @@ -331,6 +388,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x3000 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; @@ -341,6 +403,11 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x3400 0x400>; qcom,micro-idle; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + qcom,active-only; qcom,iova-width = <32>; }; };