From c25fdafc009300d593c0abdeec5498a5d6ef7fd9 Mon Sep 17 00:00:00 2001
From: Hemant Kumar <hemantk@quicinc.com>
Date: Thu, 16 Jul 2020 13:23:16 -0700
Subject: [PATCH] ARM: dts: msm: Add support to pass MSI address size on
 Lahaina

Some targets need to set the MSI address size same as the
PCIe data size(bytes) that PCIe core will halt for each write
transaction. Hence add a property to pass the exponent (base 2)
value for the size. Not setting this value same as PCIe core
write halt size results into a deadlock on system bus.

Change-Id: I9d8dd27fdb7ee25d5673a0fc96bf43f0aa6013ab
---
 qcom/lahaina-pcie.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi
index 32f0dcd3..51c7a9fc 100644
--- a/qcom/lahaina-pcie.dtsi
+++ b/qcom/lahaina-pcie.dtsi
@@ -200,6 +200,7 @@
 		compatible = "qcom,pci-msi";
 		msi-controller;
 		reg = <0x17a10040 0x0>;
+		qcom,msi-addr-size-exp = <20>;
 		interrupt-parent = <&intc>;
 		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
 			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,