From 7fafc152e4fc707947a5c27aa535207f114dd473 Mon Sep 17 00:00:00 2001
From: Chandra Sai Chidipudi <cchidipu@qti.qualcomm.com>
Date: Thu, 5 Mar 2020 17:18:31 +0530
Subject: [PATCH] ARM: dts: msm: Add IMEM entry for Shima

Add entry for system IMEM to read or write various
system level configurations.

Change-Id: I5489b7eccdd8a3a1d7357ea947ac3d7df4e767a6
---
 qcom/shima.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 2b9d6243..1131a52b 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -470,6 +470,49 @@
 		qcom,rtb-size = <0x100000>;
 	};
 
+	qcom,msm-imem@146aa000 {
+		compatible = "qcom,msm-imem";
+		reg = <0x146aa000 0x1000>;
+		ranges = <0x0 0x146aa000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		dload_type@1c {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x1c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+		pil@94c {
+			compatible = "qcom,msm-imem-pil";
+			reg = <0x94c 0xc8>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+	};
+
 	clocks {
 		xo_board: xo-board {
 			compatible = "fixed-clock";