From 7fdda6ba7b188b488c83433cc693d3dc8cfd05cf Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Mon, 24 Aug 2020 20:52:38 -0700 Subject: [PATCH] Revert "ARM: dts: msm: Add USB CSR clock entry on Lahaina" This reverts commit b92c3f5e10b6dca5075acd6702b6d4b1041cb485. Change-Id: I51e9650ee26b7a6cdc9ff881174521f5ed246dc4 --- qcom/lahaina-usb.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index d0774354..dfb0f8d3 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -29,10 +29,9 @@ <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>; + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "core_csr_clk"; + "utmi_clk", "sleep_clk"; resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; @@ -365,10 +364,9 @@ <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, - <&clock_gcc GCC_USB3_SEC_CLKREF_EN>, - <&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>; + <&clock_gcc GCC_USB3_SEC_CLKREF_EN>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "xo", "core_csr_clk"; + "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset";