From 844ff45065aa36e1eef4396f712d5a9d3279d4c6 Mon Sep 17 00:00:00 2001
From: Taniya Das <tdas@qti.qualcomm.com>
Date: Thu, 30 Sep 2021 06:13:23 +0530
Subject: [PATCH] bindings: clock: Add support for CAPE clock controllers

Add the GCC, GPUCC, CAMCC, DISPCC, VIDEOCC clock controller
bindings for CAPE device.

Change-Id: I298a3b553950d0f8b0be72efca772d2f7702ccd8
---
 bindings/clock/qcom,camcc.txt   | 1 +
 bindings/clock/qcom,dispcc.txt  | 1 +
 bindings/clock/qcom,gcc.txt     | 1 +
 bindings/clock/qcom,gpucc.txt   | 1 +
 bindings/clock/qcom,videocc.txt | 1 +
 5 files changed, 5 insertions(+)

diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt
index c6aa0684..f149a397 100644
--- a/bindings/clock/qcom,camcc.txt
+++ b/bindings/clock/qcom,camcc.txt
@@ -10,6 +10,7 @@ Required properties :
 		"qcom,waipio-camcc"
 		"qcom,waipio-camcc-v2"
 		"qcom,diwali-camcc"
+		"qcom,cape-camcc"
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
 - #reset-cells : from common reset binding, shall contain 1.
diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index 9137b858..220c97da 100644
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -11,6 +11,7 @@ Required properties :
 			"qcom,holi-dispcc"
 			"qcom,waipio-dispcc"
 			"qcom,diwali-dispcc"
+			"qcom,cape-dispcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 23707856..8d765baf 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -33,6 +33,7 @@ Required properties :
 			"qcom,sdxlemur-gcc"
 			"qcom,waipio-gcc"
 			"qcom,diwali-gcc"
+			"qcom,cape-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index 9de26b74..08c8b472 100644
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -9,6 +9,7 @@ Required properties :
 		"qcom,waipio-gpucc",
 		"qcom,waipio-gpucc-v2",
 		"qcom,diwali-gpucc".
+		"qcom,cape-gpucc",
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
 		Must contain "cc_base".
diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt
index 0dd091f5..860c9883 100644
--- a/bindings/clock/qcom,videocc.txt
+++ b/bindings/clock/qcom,videocc.txt
@@ -9,6 +9,7 @@ Required properties :
 			"qcom,shima-videocc"
 			"qcom,waipio-videocc"
 			"qcom,diwali-videocc"
+			"qcom,cape-videocc"
 
 - reg : shall contain base register location and length
 - #clock-cells : from common clock binding, shall contain 1.