From 88bbe5a617ebd0c8a8305e6b9a554a0ac1bd6f49 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Tue, 30 Nov 2021 14:47:07 +0530 Subject: [PATCH] ARM: dts: msm: Configure RX sleep state with GPIO mode for wakeup This change configures sleep state of UART RX line into GPIO mode to support the wakeup feature. Pinctrl driver and wakeup functionality expects PIN to be in gpio mode. Also add shutdown pinctrl state to reduce power during BT OFF. Change-Id: I64a34e10374f64092b202ab4f0213023049552ec --- qcom/diwali-pinctrl.dtsi | 33 ++++++++++++++++++++++++++++++--- qcom/diwali-qupv3.dtsi | 12 +++++++----- 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/qcom/diwali-pinctrl.dtsi b/qcom/diwali-pinctrl.dtsi index 058397f8..b8edd3d6 100644 --- a/qcom/diwali-pinctrl.dtsi +++ b/qcom/diwali-pinctrl.dtsi @@ -482,14 +482,14 @@ }; }; - qupv3_se7_ctsrx: qupv3_se7_ctsrx { + qupv3_se7_cts: qupv3_se7_cts { mux { - pins = "gpio28", "gpio31"; + pins = "gpio28"; function = "qup0_se7"; }; config { - pins = "gpio28", "gpio31"; + pins = "gpio28"; drive-strength = <2>; bias-disable; }; @@ -520,6 +520,33 @@ bias-pull-up; }; }; + + /* RX to be in gpio mode for sleep config */ + qupv3_se7_rx_wake: qupv3_se7_rx_wake { + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_rx_active: qupv3_se7_rx_active { + mux { + pins = "gpio31"; + function = "qup0_se7"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; }; qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { diff --git a/qcom/diwali-qupv3.dtsi b/qcom/diwali-qupv3.dtsi index 5b3e6a36..987ad296 100644 --- a/qcom/diwali-qupv3.dtsi +++ b/qcom/diwali-qupv3.dtsi @@ -348,13 +348,15 @@ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se7_default_cts>, <&qupv3_se7_default_rtsrx>, <&qupv3_se7_default_tx>; - pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, - <&qupv3_se7_tx>; - pinctrl-2 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, - <&qupv3_se7_tx>; + pinctrl-1 = <&qupv3_se7_cts>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>, <&qupv3_se7_rx_active>; + pinctrl-2 = <&qupv3_se7_cts>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>, <&qupv3_se7_rx_wake>; + pinctrl-3 = <&qupv3_se7_default_cts>, + <&qupv3_se7_default_rtsrx>, <&qupv3_se7_default_tx>; qcom,wakeup-byte = <0xFD>; qcom,wrapper-core = <&qupv3_0>; status = "disabled";