From 8d54a339f5bc63cd187514b533857f3fa1a881f9 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Mon, 30 Mar 2020 19:48:27 +0530 Subject: [PATCH] ARM: dts: msm: Add QUPv3 and GPI DT nodes on SHIMA Add QUPv3(I2C, SPI and UART) and GPI DT nodes on SHIMA. Change-Id: I27040fa93762032d76098409ac67e47a74d4a5db --- qcom/shima-pinctrl.dtsi | 964 ++++++++++++++++++++++++++++++++++++++++ qcom/shima-qupv3.dtsi | 717 ++++++++++++++++++++++++++++++ 2 files changed, 1681 insertions(+) diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index abcef61a..a947982e 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -9,6 +9,306 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio56", "gpio57"; + function = "qup8"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "qup8"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio60", "gpio61"; + function = "qup9"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "qup9"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "qup11"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "qup11"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup12"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup12"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + qupv3_se13_2uart_pins: qupv3_se13_2uart_pins { qupv3_se13_2uart_active: qupv3_se13_2uart_active { mux { @@ -36,6 +336,670 @@ }; }; }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio32", "gpio33"; + function = "qup14"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup14"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se15_4uart_pins: qupv3_se15_4uart_pins { + qupv3_se15_default_cts: + qupv3_se15_default_cts { + mux { + pins = "gpio68"; + function = "gpio"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_default_rtsrx: + qupv3_se15_default_rtsrx { + mux { + pins = "gpio69", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se15_default_tx: + qupv3_se15_default_tx { + mux { + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se15_ctsrx: qupv3_se15_ctsrx { + mux { + pins = "gpio68", "gpio71"; + function = "qup15"; + }; + + config { + pins = "gpio68", "gpio71"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_rts: qupv3_se15_rts { + mux { + pins = "gpio69"; + function = "qup15"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se15_tx: qupv3_se15_tx { + mux { + pins = "gpio70"; + function = "qup15"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio40", "gpio41"; + function = "qup0"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup0"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup1"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup1"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup2"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup2"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio48", "gpio49"; + function = "qup3"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio80"; + function = "qup3"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio52", "gpio53"; + function = "qup4"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup4"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup5"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio3", "gpio2"; + function = "qup5"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio3", "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio3", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio3", "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup6"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio14", "gpio15", + "gpio30", "gpio31"; + function = "qup6"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_2uart_pins: qupv3_se6_2uart_pins { + qupv3_se6_default_txrx: qupv3_se6_default_txrx { + mux { + pins = "gpio30", "gpio31"; + function = "qup6"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_2uart_active: qupv3_se6_2uart_active { + mux { + pins = "gpio30", "gpio31"; + function = "qup6"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup7"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup7"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; }; }; diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index 6d70a11a..d1d54be4 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -1,6 +1,25 @@ #include &soc { + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup0 0: SE 8 + * Qup0 1: SE 9 + * Qup0 2: SE 10 + * Qup0 3: SE 11 + * Qup0 4: SE 12 + * Qup0 5: SE 13 + * Qup0 6: SE 14 + * Qup0 7: SE 15 + */ + /* QUPv3_0 wrapper instance */ qupv3_0: qcom,qupv3_0_geni_se@9c0000 { compatible = "qcom,qupv3-geni-se"; @@ -14,6 +33,243 @@ qcom,iommu-dma = "fastmap"; }; + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x4d6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se8_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + /* Debug UART Instance */ qupv3_se13_2uart: qcom,qup_uart@994000 { compatible = "qcom,msm-geni-console"; @@ -30,4 +286,465 @@ qcom,wrapper-core = <&qupv3_0>; status = "ok"; }; + + qupv3_se14_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se15_4uart: qcom,qup_uart@99c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x99c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 71 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se15_default_cts>, + <&qupv3_se15_default_rtsrx>, <&qupv3_se15_default_tx>; + pinctrl-1 = <&qupv3_se15_ctsrx>, <&qupv3_se15_rts>, + <&qupv3_se15_tx>; + pinctrl-2 = <&qupv3_se15_ctsrx>, <&qupv3_se15_rts>, + <&qupv3_se15_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x43 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x56 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + qcom,shared; + status = "disabled"; + }; + + qupv3_se5_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* Travel adapter over 2-wire HSUART, no wakeup */ + qupv3_se6_2uart: qcom,qup_uart@a98000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa98000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se6_default_txrx>; + pinctrl-1 = <&qupv3_se6_2uart_active>; + pinctrl-2 = <&qupv3_se6_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma1 0 7 3 64 0>, + <&gpi_dma1 1 7 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a9c000 { + compatible = "qcom,spi-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma1 0 7 1 64 0>, + <&gpi_dma1 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + };