From 29f936c130955323c5541b07880b31fb9483aeb6 Mon Sep 17 00:00:00 2001
From: Yue Liu <yueliu@qti.qualcomm.com>
Date: Fri, 28 Oct 2022 15:39:21 +0800
Subject: [PATCH] ARM: dts: msm: Add next-level-cache for core 4 on Ravelin

Add next-level-cache for core 4 on Ravelin.

Change-Id: I6edbebce922e8f8e44effa990e17083607d6622c
---
 qcom/ravelin.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi
index 50b47ee2..37ec78a3 100644
--- a/qcom/ravelin.dtsi
+++ b/qcom/ravelin.dtsi
@@ -135,6 +135,7 @@
 			cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
 			power-domains = <&CPU_PD4>;
 			power-domain-names = "psci";
+			next-level-cache = <&L2_4>;
 			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0 6>;
 			L2_4: l2-cache {