diff --git a/qcom/anorak-pinctrl.dtsi b/qcom/anorak-pinctrl.dtsi
index cc6ac4d6..489e4281 100644
--- a/qcom/anorak-pinctrl.dtsi
+++ b/qcom/anorak-pinctrl.dtsi
@@ -27,6 +27,58 @@
 		};
 	};
 
+	sdc2_on: sdc2_on {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		sd-cd {
+			pins = "gpio175";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+
+	sdc2_off: sdc2_off {
+		clk {
+			pins = "sdc2_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc2_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc2_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		sd-cd {
+			pins = "gpio175";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+	};
+
 	pcie0 {
 		pcie0_perst_default: pcie0_perst_default {
 			mux {
diff --git a/qcom/anorak-rumi.dtsi b/qcom/anorak-rumi.dtsi
index 1551d2b3..0246a267 100644
--- a/qcom/anorak-rumi.dtsi
+++ b/qcom/anorak-rumi.dtsi
@@ -1,4 +1,5 @@
 #include <dt-bindings/clock/qcom,gcc-anorak.h>
+#include <dt-bindings/gpio/gpio.h>
 
 &arch_timer {
 	clock-frequency = <500000>;
@@ -101,6 +102,25 @@
 	};
 };
 
+&sdhc_2 {
+	status = "ok";
+	vdd-supply = <&L12B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&L18B>;
+	qcom,vdd-io-voltage-level = <2960000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	is_rumi;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+};
+
 &ufsphy_mem {
 	compatible = "qcom,ufs-phy-qrbtc-sdm845";
 
diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi
index 78e13c7b..c8593172 100644
--- a/qcom/anorak.dtsi
+++ b/qcom/anorak.dtsi
@@ -40,6 +40,7 @@
 
 	aliases {
 		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
+		mmc1 = &sdhc_2; /* SDC2 SD card slot */
 		serial0 = &qupv3_se6_2uart;
 	};
 
@@ -1270,6 +1271,64 @@
 		qcom,low-latency;
 	};
 
+	sdhc2_opp_table: sdhc2-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-peak-kBps = <1600000 280000>;
+			opp-avg-kBps = <50000 0>;
+		};
+
+		opp-202000000 {
+			opp-hz = /bits/ 64 <202000000>;
+			opp-peak-kBps = <5600000 1500000>;
+			opp-avg-kBps = <104000 0>;
+		};
+	};
+
+	sdhc_2: sdhci@8804000 {
+		status = "disabled";
+
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x08804000 0x1000>;
+		reg-names = "hc";
+
+		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		bus-width = <4>;
+		no-sdio;
+		no-mmc;
+
+		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+			<&gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface", "core";
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642C 0x0 0x10
+					0x2C010800 0x80040868>;
+
+		iommus = <&apps_smmu 0x420 0x0>;
+		dma-coherent;
+		qcom,iommu-dma = "fastmap";
+
+		interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
+		interconnect-names = "sdhc-ddr","cpu-sdhc";
+		operating-points-v2 = <&sdhc2_opp_table>;
+
+		qos0 {
+			mask = <0xf0>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0x03>;
+			vote = <44>;
+		};
+	};
 
 	ufsphy_mem: ufsphy_mem@1d87000 {
 		reg = <0x1d87000 0xe10>;