From df706f98e9eb15b29bfd28b527b4f0110b5337d8 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Tue, 9 Aug 2022 02:53:05 +0530 Subject: [PATCH] ARM: dts: msm: update phy compatible for anarok phy Update phy compatible for Anarok phy driver. Change-Id: I87b30020ef9fcd3fb0e0e302b426b64adb9d5926 --- qcom/anorak-idp.dtsi | 5 +---- qcom/anorak-qxr.dtsi | 5 +---- qcom/anorak.dtsi | 17 +++++++++++++---- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/qcom/anorak-idp.dtsi b/qcom/anorak-idp.dtsi index 57819591..035e5c48 100644 --- a/qcom/anorak-idp.dtsi +++ b/qcom/anorak-idp.dtsi @@ -24,7 +24,7 @@ &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-anorak"; + compatible = "qcom,ufs-phy-qmp-v4-anarok"; vdda-phy-supply = <&L2F>; vdda-pll-supply = <&L2C>; @@ -43,9 +43,6 @@ vccq-supply = <&L3B>; vccq-max-microamp = <1200000>; - vccq2-supply = <&L3F>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L3B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/anorak-qxr.dtsi b/qcom/anorak-qxr.dtsi index 4fe66055..6ef4850b 100644 --- a/qcom/anorak-qxr.dtsi +++ b/qcom/anorak-qxr.dtsi @@ -23,7 +23,7 @@ }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-anorak"; + compatible = "qcom,ufs-phy-qmp-v4-anarok"; vdda-phy-supply = <&L2F>; vdda-pll-supply = <&L2C>; @@ -42,9 +42,6 @@ vccq-supply = <&L3B>; vccq-max-microamp = <1200000>; - vccq2-supply = <&L3F>; - vccq2-max-microamp = <800000>; - qcom,vddp-ref-clk-supply = <&L3B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi index 5dbc297a..b883bd7d 100644 --- a/qcom/anorak.dtsi +++ b/qcom/anorak.dtsi @@ -2292,10 +2292,19 @@ lanes-per-direction = <2>; clock-names = "ref_clk_src", "ref_aux_clk", - "qref_clk"; + "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_UFS_0_CLKREF_EN>; + <&gcc GCC_UFS_0_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; status = "disabled"; }; @@ -2415,13 +2424,13 @@ status = "disabled"; qos0 { - mask = <0xf0>; + mask = <0x30>; vote = <44>; perf; }; qos1 { - mask = <0x03>; + mask = <0x0f>; vote = <44>; }; };