From 9f853f5b6db7c86f902bf4d6d8389486f0f161d6 Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Mon, 1 Nov 2021 18:04:58 +0530
Subject: [PATCH] ARM: dts: msm: Add PDC, apps_rsc and disp_rsc devices for
 parrot

Add PDC irq chip, apps_rsc and disp_rsc devices to enable RPMH
communication.

Change-Id: I1d36d5b0ab0ce643b7946e85da0be113fc5f290a
---
 qcom/parrot-pinctrl.dtsi |  1 +
 qcom/parrot-rumi.dtsi    |  3 +++
 qcom/parrot.dtsi         | 48 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 52 insertions(+)

diff --git a/qcom/parrot-pinctrl.dtsi b/qcom/parrot-pinctrl.dtsi
index 6c799751..5054dcd2 100644
--- a/qcom/parrot-pinctrl.dtsi
+++ b/qcom/parrot-pinctrl.dtsi
@@ -7,6 +7,7 @@
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
 	};
 
 	sdc1_on: sdc1_on {
diff --git a/qcom/parrot-rumi.dtsi b/qcom/parrot-rumi.dtsi
index 7ac913e2..0bb790b5 100644
--- a/qcom/parrot-rumi.dtsi
+++ b/qcom/parrot-rumi.dtsi
@@ -31,6 +31,9 @@
 		     0x0 0x4>;
 	};
 
+	disp_rsc: rsc@af20000 {
+		status = "disabled";
+	};
 };
 
 &usb0 {
diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi
index e65eb299..81511470 100644
--- a/qcom/parrot.dtsi
+++ b/qcom/parrot.dtsi
@@ -2,6 +2,7 @@
 #include <dt-bindings/interconnect/qcom,parrot.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,camcc-parrot.h>
 #include <dt-bindings/clock/qcom,dispcc-parrot.h>
@@ -261,6 +262,53 @@
 		clock-frequency = <19200000>;
 	};
 
+	apps_rsc: rsc@17a00000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x17a00000 0x10000>,
+		      <0x17a10000 0x10000>,
+		      <0x17a20000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0xd00>;
+		qcom,drv-id = <2>;
+		qcom,tcs-config = <ACTIVE_TCS    3>,
+				  <SLEEP_TCS     2>,
+				  <WAKE_TCS      2>,
+				  <CONTROL_TCS   0>, /* PDC wakeup values will be written from TZ */
+				  <FAST_PATH_TCS 1>;
+
+	};
+
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
+		reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
+		qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+				  <125 63 1>, <126 716 12>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+		qcom,tcs-offset = <0x1c00>;
+		qcom,drv-id = <0>;
+		qcom,tcs-config = <ACTIVE_TCS    0>,
+				  <SLEEP_TCS     1>,
+				  <WAKE_TCS      1>,
+				  <CONTROL_TCS   0>,
+				  <FAST_PATH_TCS 0>;
+	};
+
 	memtimer: timer@17420000 {
 		#address-cells = <1>;
 		#size-cells = <1>;