From 98e77f01404d7dc79abb699be724754a186d5a7c Mon Sep 17 00:00:00 2001
From: Jagadeesh Kona <jkona@qti.qualcomm.com>
Date: Mon, 26 Jul 2021 13:04:56 +0530
Subject: [PATCH] ARM: dts: msm: Update VIDEOCC clock node for DIWALI

Update Video Clock Controller node for DIWALI platform.

Change-Id: Ia806dc1be874ba5649c0f559b2854b007d0159b6
---
 qcom/diwali-rumi.dtsi |  7 +++++++
 qcom/diwali.dtsi      | 14 +++++++++++---
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/qcom/diwali-rumi.dtsi b/qcom/diwali-rumi.dtsi
index db7573f2..92865883 100644
--- a/qcom/diwali-rumi.dtsi
+++ b/qcom/diwali-rumi.dtsi
@@ -96,3 +96,10 @@
 &qupv3_se5_2uart {
 	qcom,rumi_platform;
 };
+
+&videocc {
+	clocks = <&bi_tcxo>,
+		<&bi_tcxo_ao>,
+		<&sleep_clk>,
+		<&gcc GCC_VIDEO_AHB_CLK>;
+};
diff --git a/qcom/diwali.dtsi b/qcom/diwali.dtsi
index 9701d0dc..a4b01441 100644
--- a/qcom/diwali.dtsi
+++ b/qcom/diwali.dtsi
@@ -710,9 +710,17 @@
 		#reset-cells = <1>;
 	};
 
-	videocc: clock-controller@abf0000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "videocc_clocks";
+	videocc: clock-controller@aaf0000 {
+		compatible = "qcom,diwali-videocc", "syscon";
+		reg = <0xaaf0000 0x10000>;
+		reg-name = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&rpmhcc RPMH_CXO_CLK_A>,
+			<&sleep_clk>,
+			<&gcc GCC_VIDEO_AHB_CLK>;
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};