From 9c8dcecc4d3801a3de3c667ace1dccff6c1884f5 Mon Sep 17 00:00:00 2001
From: Ram Chandrasekar <rkumbako@quicinc.com>
Date: Fri, 8 May 2020 11:19:02 -0700
Subject: [PATCH] dt-bindings: thermal: sdpm: Add SDPM clock monitor bindings

SDPM driver will monitor different clocks and write the clock rate into
the respective CSR register. This document explains the devicetree
properties required by this driver.

Change-Id: Ieb8efb83cc130716839a6830e104a3c951edb1b2
---
 bindings/thermal/qcom-sdpm.txt | 57 ++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 bindings/thermal/qcom-sdpm.txt

diff --git a/bindings/thermal/qcom-sdpm.txt b/bindings/thermal/qcom-sdpm.txt
new file mode 100644
index 00000000..8a0a0f9f
--- /dev/null
+++ b/bindings/thermal/qcom-sdpm.txt
@@ -0,0 +1,57 @@
+Simple Digital Power Meter(SDPM) clock monitoring.
+
+SDPM is used to monitor the operating frequency of different clocks and based
+on operating levels of different clients, the Policy Engine will recommend a
+new max operating level. The SDPM driver will register with the clock
+framework for rate change notification of different clocks. These clock rate
+will be updated to SDPM.
+
+Properties:
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be "qcom,sdpm"
+
+- reg:
+	Usage: required
+	Value type: <u32>
+	Definition: RDPM base address.
+
+- clocks:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: A List of phandle and clock specifier pairs as listed
+			in clock-names property.
+
+- clock-names:
+	Usage: required
+	Value type: <stringlist>
+	Definition: List of clock names matching the clock order mentioned in
+			the clocks property.
+- cpu:
+	Usage: optional
+	Value type: <CPU phandle>
+	Definition: The CPU for which the clock changes should be monitored.
+
+- csr-id:
+	Usage: required
+	Value type: <array of u32>
+	Definition: Array of CSR ID matching the clock order mentioned in the
+			clocks property. The last ID can be the CSR
+			corresponding to the CPU that needs to be monitored.
+
+Example:
+
+cx_sdpm@0x00634000 {
+	compatible = "qcom,sdpm";
+	reg = <0x00634000 0x1000>;
+	clock-names = "cam_cc", "compo_aux";
+	clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
+		<&clk_m_a2_div1 CLK_M_COMPO_AUX>;
+	cpu = <&CPU7>;
+	csr-id = <5 7 4>;
+	//CSR 5 <=> cam_cc
+	//CSR 7 <=> compo_aux
+	//CSR 4 <=> CPU7
+};