From 9dfc53d319ba18669e02f75c584c772832859bcc Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Wed, 24 May 2023 09:44:25 +0800 Subject: [PATCH] ARM: dts: msm: Add new core-hang info property Current properties "qcom,threshold-arr" and "qcom,config-arr" assumes that logical CPU number & physical CPU has 1:1 mapping and accordingly all the registers placed linearly with increasing order of logical CPU numbers. But if any CPU is not available then 1:1 mapping is broken as we are having logically contiguous CPU numbers even if physical cpus are not available. To resolve this we are replacing old properties with a new property "qcom,chd-percpu-info" and map core-hang registers wrt to CPU phandles. The format is <&CPUx_Phandle CPUx_Threshold CPUx_Config>. Change-Id: I17864c4e5b0a2739cf60e3dd2fdc264f778c083e --- qcom/ravelin.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index b30a8046..5ffcdb1b 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1272,10 +1272,14 @@ qcom,chd { compatible = "qcom,core-hang-detect"; label = "core"; - qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 - 0x17840058 0x17850058 0x17860058 0x17870058>; - qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 - 0x17840060 0x17850060 0x17860060 0x17870060>; + qcom,chd-percpu-info = <&CPU0 0x17800058 0x17800060>, + <&CPU1 0x17810058 0x17810060>, + <&CPU2 0x17820058 0x17820060>, + <&CPU3 0x17830058 0x17830060>, + <&CPU4 0x17840058 0x17840060>, + <&CPU5 0x17850058 0x17850060>, + <&CPU6 0x17860058 0x17860060>, + <&CPU7 0x17870058 0x17870060>; }; qcom_cedev: qcedev@1de0000 {