From 121ae6454a1f0005c7acc1d772443c8b1ea6b0b4 Mon Sep 17 00:00:00 2001
From: Sandeep Singh <sandsing@qti.qualcomm.com>
Date: Thu, 3 Nov 2022 14:11:58 +0530
Subject: [PATCH] ARM: dts: msm: Add wpss node for ravelin

Add wpss node for ravelin to enable wpss fw loading.

Change-Id: I333b7fc4d1c222470ac9e50f01c05b9a9a15173d
---
 bindings/remoteproc/qcom,adsp.txt |  1 +
 qcom/ravelin.dtsi                 | 63 +++++++++++++++++++++++++++++++
 2 files changed, 64 insertions(+)

diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt
index e875e407..35496ecd 100644
--- a/bindings/remoteproc/qcom,adsp.txt
+++ b/bindings/remoteproc/qcom,adsp.txt
@@ -47,6 +47,7 @@ on the Qualcomm ADSP Hexagon core.
 		    "qcom,anorak-cdsp-pas"
 		    "qcom,ravelin-adsp-pas"
 		    "qcom,ravelin-modem-pas"
+		    "qcom,ravelin-wpss-pas"
 
 
 - interrupts-extended:
diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi
index 64e20f49..7e1f9d6e 100644
--- a/qcom/ravelin.dtsi
+++ b/qcom/ravelin.dtsi
@@ -1581,6 +1581,69 @@
 			};
 		};
 	};
+
+	wpss_pas: remoteproc-wpss@8a00000 {
+		compatible = "qcom,ravelin-wpss-pas";
+		reg = <0x08a00000 0x10000>;
+		status = "ok";
+
+		memory-region = <&wpss_moselle_mem>;
+		firmware-name = "adrastea/wpss.mdt";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MX_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx","mx";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		/* Inputs from wpss */
+		interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+				      <&wpss_smp2p_in 0 0>,
+				      <&wpss_smp2p_in 2 0>,
+				      <&wpss_smp2p_in 1 0>,
+				      <&wpss_smp2p_in 3 0>,
+				      <&wpss_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				   "fatal",
+				   "handover",
+				   "ready",
+				   "stop-ack",
+				   "shutdown-ack";
+
+		/* Outputs to wpss */
+		qcom,smem-states = <&wpss_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			qcom,remote-pid = <13>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "wpss_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_WPSS
+					  IPCC_MPROC_SIGNAL_GLINK_QMP
+					  IRQ_TYPE_EDGE_RISING>;
+
+			label = "wpss";
+			qcom,glink-label = "wpss";
+
+			qcom,wpss_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+		};
+	};
+
 	qcom,msm_gsi {
 		compatible = "qcom,msm_gsi";
 	};