diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 02fc1704..c1ae70ff 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -20,6 +20,7 @@ conditions. "qcom,qsmmu-v500" "qcom,adreno-smmu" "qcom,smmu-v2" + "qcom,virt-smmu" depending on the particular implementation and/or the version of the architecture implemented. @@ -33,6 +34,12 @@ conditions. as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + "qcom,virt-smmu" is a subtype of "qcom,qsmmu-v500" which + only supports access to the set of registers required by + the arm specificiation. None of the additional registers + normally present in qcom,qsmmu-v500 are supported + currently. + - reg : Base address and size of the SMMU. - reg-names : For the "qcom,qsmmu-v500" device "tcu-base" is expected. diff --git a/qcom/msm-arm-smmu-waipio-vm.dtsi b/qcom/msm-arm-smmu-waipio-vm.dtsi new file mode 100644 index 00000000..4d79e094 --- /dev/null +++ b/qcom/msm-arm-smmu-waipio-vm.dtsi @@ -0,0 +1,31 @@ +#include + +/ { + vm-config { + vdevices { + vsmmu@15000000 { + vdevice-type = "vsmmu-v2"; + smmu-handle = <0x15000000>; + num-cbs = <0x2>; + num-smrs = <0x3>; + patch = "/soc/apps-smmu@15000000"; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@15000000 { + /* + * reg, #global-interrupts & interrupts properties will + * be added dynamically by bootloader. + */ + compatible = "qcom,qsmmu-v500", "qcom,virt-smmu"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + dma-coherent; + qcom,actlr = + <0x2803 0x0400 0x00000001>, + <0x2804 0x0402 0x00000001>; + }; +}; diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index 462b1377..cb851054 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -369,3 +369,4 @@ }; #include "waipio-vm-dma-heaps.dtsi" +#include "msm-arm-smmu-waipio-vm.dtsi"