From a4e74f3ebd2bf3fd04d7acb452ae9b3f4cbd00a0 Mon Sep 17 00:00:00 2001
From: Kamal Agrawal <kamaagra@qti.qualcomm.com>
Date: Fri, 20 Jan 2023 16:34:27 +0530
Subject: [PATCH] ARM: dts: msm: Enable GPU's fuse read support for Anorak

Enable GPU's fuse read support for Anorak.

Change-Id: I8fc4000d856a886fddfb746abd441b7d1794f9ee
---
 qcom/anorak-gpu.dtsi |  3 +++
 qcom/anorak.dtsi     | 11 +++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/qcom/anorak-gpu.dtsi b/qcom/anorak-gpu.dtsi
index a44c3554..0d0b2426 100644
--- a/qcom/anorak-gpu.dtsi
+++ b/qcom/anorak-gpu.dtsi
@@ -66,6 +66,9 @@
 			<MHZ_TO_KBPS(2736, 4)>, /* index=8  */
 			<MHZ_TO_KBPS(3867, 4)>; /* index=9  */
 
+		nvmem-cells = <&gpu_speed_bin>;
+		nvmem-cell-names = "speed_bin";
+
 		zap-shader {
 			memory-region = <&gpu_microcode_mem>;
 		};
diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi
index 8493fb31..025ac289 100644
--- a/qcom/anorak.dtsi
+++ b/qcom/anorak.dtsi
@@ -2670,15 +2670,22 @@
 		feat_conf11: feat_conf11@12c {
 			reg = <0x12c 0x4>;
 		};
+
+		gpu_speed_bin: gpu_speed_bin@119 {
+			reg = <0x119 0x2>;
+			bits = <7 8>;
+		};
 	};
 
 	qfprom_sys: qfprom@0 {
 		compatible = "qcom,qfprom-sys";
 
 		nvmem-cells = <&feat_conf10>,
-				<&feat_conf11>;
+				<&feat_conf11>,
+				<&gpu_speed_bin>;
 		nvmem-cell-names = "feat_conf10",
-				"feat_conf11";
+				"feat_conf11",
+				"gpu_speed_bin";
 	};
 
 	eud: qcom,msm-eud@88e0000 {