From a6bcbbe573bb6235c9d3ff04d4719d3114786801 Mon Sep 17 00:00:00 2001
From: Shivnandan Kumar <kshivnan@qti.qualcomm.com>
Date: Thu, 20 Oct 2022 10:39:22 +0530
Subject: [PATCH] ARM: dts: msm: enable rimps, scmi node

Enable rimps, scmi  and sram node in
anorak.

Change-Id: I1b9ec85ec9cb8bc72945bd2f3953c34cb183fd22
---
 qcom/anorak.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi
index 171d6d6b..f20fd2ff 100644
--- a/qcom/anorak.dtsi
+++ b/qcom/anorak.dtsi
@@ -274,6 +274,19 @@
 
 	soc: soc { };
 
+	sram: sram@17D09100 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "mmio-sram";
+		reg = <0x0 0x17D09100 0x0 0x200>;
+		ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>;
+
+		cpu_scp_lpri: scp-shmem@0 {
+			compatible = "arm,scp-shmem";
+			reg = <0x0 0x0 0x0 0x200>;
+		};
+	};
+
 	firmware: firmware { };
 };
 
@@ -1291,6 +1304,8 @@
 
 	qcom_pmu: qcom,pmu {
 		compatible = "qcom,pmu";
+		reg = < 0x17D09300 0x300>;
+		reg-names = "pmu-base";
 		qcom,pmu-events-tbl =
 			< 0x0008 0x3F 0xFF 0x02 >,
 			< 0x0011 0x3F 0xFF 0x00 >,
@@ -1622,6 +1637,43 @@
 		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
 	};
 
+
+	rimps: qcom,rimps@17400000 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "qcom,rimps";
+		reg =   <0x17400000 0x10>,
+			<0x17d90000 0x2000>;
+		#mbox-cells = <1>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	scmi: qcom,scmi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "arm,scmi";
+		mboxes = <&rimps 0>;
+		mbox-names = "tx";
+		shmem = <&cpu_scp_lpri>;
+
+		scmi_plh: protocol@81 {
+			reg = <0x81>;
+			#clock-cells = <1>;
+		};
+
+		scmi_pmu: protocol@86 {
+			reg = <0x86>;
+			#clock-cells = <1>;
+		};
+
+	};
+
+	rimps_log: qcom,rimps_log@17d09c00 {
+		compatible = "qcom,rimps-log";
+		reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>;
+		mboxes = <&rimps 1>;
+	};
+
 	ipcc_mproc: qcom,ipcc@ed18000 {
 		compatible = "qcom,ipcc";
 		reg = <0x408000 0x1000>;