From bd4ea97ea6c3fc7baffbcd375b2091cf8595f39f Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Fri, 28 Aug 2020 15:25:46 -0700 Subject: [PATCH 1/2] bindings: clock: Update dispcc clock controller binding strings for WAIPIO Update dispcc clock controller bindings for WAIPIO device. Change-Id: Ie0218053eef62c2cedac5a6ac21d8fe4b46b0467 --- bindings/clock/qcom,dispcc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt index feaccf64..27467055 100644 --- a/bindings/clock/qcom,dispcc.txt +++ b/bindings/clock/qcom,dispcc.txt @@ -9,6 +9,7 @@ Required properties : "qcom,lahaina-dispcc" "qcom,shima-dispcc" "qcom,holi-dispcc" + "qcom,waipio-dispcc" - reg : shall contain base register location and length. - #clock-cells : from common clock binding, shall contain 1. From 73f8ec51c82b6aea901c23448605ed2fffad2dc1 Mon Sep 17 00:00:00 2001 From: Vivek Aknurwar Date: Fri, 28 Aug 2020 15:26:40 -0700 Subject: [PATCH 2/2] ARM: dts: msm: Update and enable dispcc clock controller on WAIPIO Update device tree node for dispcc and enable peripheral display controller clock driver on WAIPIO. Also enable required GDSCs. Change-Id: Idf40106f59534552652e7ac19970fcef33302752 --- qcom/waipio.dtsi | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/qcom/waipio.dtsi b/qcom/waipio.dtsi index 23d496c0..d46c90d0 100644 --- a/qcom/waipio.dtsi +++ b/qcom/waipio.dtsi @@ -572,15 +572,29 @@ /* DISP_CC GDSCs */ disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xaf09000 0x4>; regulator-name = "disp_cc_mdss_core_gdsc"; qcom,gds-timeout = <500>; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; }; disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xaf0b000 0x4>; regulator-name = "disp_cc_mdss_core_int2_gdsc"; qcom,gds-timeout = <500>; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; }; gcc_apcs_gdsc_vote_ctrl: syscon@162128 { @@ -799,9 +813,13 @@ #reset-cells = <1>; }; - clock_dispcc: qcom,dispcc { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + clock_dispcc: qcom,dispcc@af00000 { + compatible = "qcom,waipio-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; };