From f859ed4039456f717efec44a8b86b54eceada2a8 Mon Sep 17 00:00:00 2001
From: Chandana Kishori Chiluveru <cchiluve@qti.qualcomm.com>
Date: Sun, 5 Apr 2020 18:21:21 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3_0 and SE5 dt nodes for SHIMA

Add QUPv3_0 device tree changes for console UART on shima.

Change-Id: I5bd43c26d38d8118d9a7fa13706ebc8df5566fd1
---
 qcom/shima-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++
 qcom/shima-qupv3.dtsi   | 33 +++++++++++++++++++++++++++++++++
 qcom/shima.dtsi         |  1 +
 3 files changed, 62 insertions(+)
 create mode 100644 qcom/shima-qupv3.dtsi

diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi
index c828f6cc..abcef61a 100644
--- a/qcom/shima-pinctrl.dtsi
+++ b/qcom/shima-pinctrl.dtsi
@@ -8,6 +8,34 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		wakeup-parent = <&pdc>;
+
+		qupv3_se13_2uart_pins: qupv3_se13_2uart_pins {
+			qupv3_se13_2uart_active: qupv3_se13_2uart_active {
+				mux {
+					pins = "gpio18", "gpio19";
+					function = "qup13";
+				};
+
+				config {
+					pins = "gpio18", "gpio19";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep {
+				mux {
+					pins = "gpio18", "gpio19";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio18", "gpio19";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
 	};
 };
 
diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi
new file mode 100644
index 00000000..6d70a11a
--- /dev/null
+++ b/qcom/shima-qupv3.dtsi
@@ -0,0 +1,33 @@
+#include <dt-bindings/interconnect/qcom,shima.h>
+
+&soc {
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-bus-ids =
+			<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
+			<MASTER_QUP_0 SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x4c3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-dma = "fastmap";
+	};
+
+	/* Debug UART Instance */
+	qupv3_se13_2uart: qcom,qup_uart@994000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0x994000 0x4000>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_2uart_active>;
+		pinctrl-1 = <&qupv3_se13_2uart_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "ok";
+	};
+};
diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 0df1a4d7..70224919 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -1131,6 +1131,7 @@
 #include "shima-pinctrl.dtsi"
 #include "shima-pm.dtsi"
 #include "shima-stub-regulator.dtsi"
+#include "shima-qupv3.dtsi"
 #include "shima-gdsc.dtsi"
 #include "shima-ion.dtsi"
 #include "shima-usb.dtsi"