From bd91dc5af1e95f45bfe98a9552da1a184ca9efce Mon Sep 17 00:00:00 2001 From: Kalpak Kawadkar Date: Wed, 13 Jul 2022 16:46:08 +0530 Subject: [PATCH] ARM: dts: msm: Update GPUCC node and its gdsc's for RAVELIN Update graphics clock controller node and its corresponding gdsc's for RAVELIN platform. Change-Id: I6973e5888eb9b654f75e879d6c50fa3b57d266e5 --- qcom/ravelin-rumi.dtsi | 7 +++++++ qcom/ravelin.dtsi | 21 +++++++++++++++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi index 4685edf9..4da3b625 100644 --- a/qcom/ravelin-rumi.dtsi +++ b/qcom/ravelin-rumi.dtsi @@ -187,3 +187,10 @@ clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>; }; + +&gpucc { + clocks = <&bi_tcxo>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; +}; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 4b884e88..35efc608 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -746,8 +746,17 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,ravelin-gpucc", "syscon"; + reg = <0x3d90000 0xa000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "bi_tcxo", "gpll0_out_main", + "gpll0_out_main_div", "gcc_gpu_snoc_dvm_gfx_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1442,12 +1451,16 @@ }; &gpu_cc_cx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gpu_cc_gx_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; sw-reset = <&gpu_cc_gx_sw_reset>; status = "ok"; };