From d0ed43579fb8d3e40b45960bdc36cf51baf0667d Mon Sep 17 00:00:00 2001
From: Sachin Kumar Garg <sachinku@qti.qualcomm.com>
Date: Fri, 7 Oct 2022 13:00:25 +0530
Subject: [PATCH] ARM: dts: msm: add support for monaco platform

Add device tree files for monaco platform.

Change-Id: I682862d0e7ec980b604adf88fab6323c7fb1e4c0
---
 Kbuild           |   4 ++
 monaco-vidc.dts  |  16 ++++++
 monaco-vidc.dtsi | 126 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 146 insertions(+)
 create mode 100644 monaco-vidc.dts
 create mode 100644 monaco-vidc.dtsi

diff --git a/Kbuild b/Kbuild
index d69de6b6..41e56db5 100644
--- a/Kbuild
+++ b/Kbuild
@@ -26,6 +26,10 @@ ifeq ($(CONFIG_ARCH_RAVELIN), y)
 dtbo-y += ravelin-vidc.dtbo
 endif
 
+ifeq ($(CONFIG_ARCH_MONACO), y)
+dtbo-y += monaco-vidc.dtbo
+endif
+
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
 clean-files    := *.dtb *.dtbo
diff --git a/monaco-vidc.dts b/monaco-vidc.dts
new file mode 100644
index 00000000..d8af8ae6
--- /dev/null
+++ b/monaco-vidc.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-monaco.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+#include <dt-bindings/clock/qcom,gpucc-monaco.h>
+#include "monaco-vidc.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. monaco SoC";
+	compatible = "qcom,monaco";
+	qcom,msm-id = <486 0x10000>, <517 0x10000>;
+	qcom,board-id = <0 0>;
+};
+
diff --git a/monaco-vidc.dtsi b/monaco-vidc.dtsi
new file mode 100644
index 00000000..5f2ecd36
--- /dev/null
+++ b/monaco-vidc.dtsi
@@ -0,0 +1,126 @@
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	msm_vidc: qcom,vidc@5a00000 {
+		compatible = "qcom,msm-vidc", "qcom,msm-vidc-monaco", "qcom,msm-vidc-ar50lt";
+		status = "okay";
+		reg = <0x5a00000 0x200000>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&intc>;
+
+		memory-region = <&video_mem>;
+		pas-id = <9>;
+
+		/* IOMMU Config */
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Supply */
+		venus-supply = <&gcc_venus_gdsc>;
+		venus-core0-supply = <&gcc_vcodec0_gdsc>;
+
+		/* Clocks */
+		clock-names = "core_clk", "iface_clk", "bus_clk",
+			"core0_clk", "core0_bus_clk", "throttle_clk";
+
+		clock-ids = <GCC_VIDEO_VENUS_CTL_CLK GCC_VIDEO_AHB_CLK
+			GCC_VENUS_CTL_AXI_CLK GCC_VIDEO_VCODEC0_SYS_CLK
+			GCC_VCODEC0_AXI_CLK GCC_VIDEO_THROTTLE_CORE_CLK>;
+		clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+			<&gcc GCC_VIDEO_AHB_CLK>,
+			<&gcc GCC_VENUS_CTL_AXI_CLK>,
+			<&gcc GCC_VIDEO_VCODEC0_SYS_CLK>,
+			<&gcc GCC_VCODEC0_AXI_CLK>,
+			<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+		qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk",
+			"core0_clk", "core0_bus_clk", "throttle_clk";
+		qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>;
+		qcom,allowed-clock-rates = <133330000 240000000>;
+
+		qcom,reg-presets = <0xB0080 0x0 0x03>;
+
+		/* Video Firmware ELF image name */
+		vidc,firmware-name = "venus_v6";
+
+		/* Buses */
+		bus_cnoc {
+			compatible = "qcom,msm-vidc,bus";
+			label = "cnoc";
+			qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+			qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+			qcom,mode = "performance";
+			qcom,bus-range-kbps = <1000 1000>;
+		};
+
+		venus_bus_ddr {
+			compatible = "qcom,msm-vidc,bus";
+			label = "venus-ddr";
+			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+			qcom,mode  = "vidc-ar50-ddr";
+			qcom,bus-range-kbps = <1000 2128000>;
+		};
+
+		arm9_bus_ddr {
+			compatible = "qcom,msm-vidc,bus";
+			label = "venus-arm9-ddr";
+			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+			qcom,mode = "performance";
+			qcom,bus-range-kbps = <1000 1000>;
+		};
+
+		/* MMUs */
+		non_secure_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_ns";
+			iommus =
+				<&apps_smmu 0x860 0x00>,
+				<&apps_smmu 0x880 0x00>;
+			qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>;
+			qcom,iommu-faults = "non-fatal";
+			buffer-types = <0xfff>;
+			virtual-addr-pool = <0x70800000 0x6f800000>;
+		};
+
+		secure_bitstream_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_bitstream";
+			iommus =
+				<&apps_smmu 0x861 0x04>;
+			qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+			buffer-types = <0x241>;
+			virtual-addr-pool = <0x4b000000 0x25800000>;
+			qcom,secure-context-bank;
+		};
+
+		secure_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_pixel";
+			iommus =
+				<&apps_smmu 0x863 0x0>;
+			qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+			buffer-types = <0x106>;
+			virtual-addr-pool = <0x25800000 0x25800000>;
+			qcom,secure-context-bank;
+		};
+
+		secure_non_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_non_pixel";
+			iommus =
+				<&apps_smmu 0x804 0xE0>;
+			qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+			buffer-types = <0x480>;
+			virtual-addr-pool = <0x1000000 0x24800000>;
+			qcom,secure-context-bank;
+		};
+	};
+};
+