From 02e9cae6bce45d220686ddc077812890d2571230 Mon Sep 17 00:00:00 2001 From: Nadav Levintov Date: Thu, 23 Apr 2020 14:04:04 +0300 Subject: [PATCH 1/2] ARM: dts: msm: add qcom,ipa-gpi_event_rp_ddr property Added a new property, which will determine if event ring RP would be read from event context register or from DDR location. Change-Id: I171cb2fad87008ef2bda8752e498ecb932f4dfc8 --- qcom/lahaina.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index a38cdcb8..7251c843 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4349,6 +4349,7 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,tx-wrapper-cache-max-size = <400>; + qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; clocks = <&clock_rpmh RPMH_IPA_CLK>; qcom,interconnect,num-cases = <5>; From 7deb8bc13dcc85274b7ef038e45c8be122be7dfa Mon Sep 17 00:00:00 2001 From: Nadav Levintov Date: Mon, 27 Apr 2020 09:29:38 +0300 Subject: [PATCH 2/2] dt-bindings: Add support for event RP access from DDR for GPI and GCI Update documentation binding to support the new property of EV RP from DDR for GPI and GCI. Change-Id: Idbf809f53876da32eac3fd3ea98f158e37897b1f --- bindings/platform/msm/ipa.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 33b9910a..14f68df2 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -118,6 +118,8 @@ memory allocation over a PCIe bridge 0 (use scm call), 1 (override scm call as though it returned true), and 2 (override scm call as though it returned false) +- qcom,ipa-gpi-event-rp-ddr: Boolean context flag to control whether GPI and GCI event + rings read pointer should be read from the ddr. IPA pipe sub nodes (A2 static pipes configurations):