diff --git a/qcom/anorak-rumi.dtsi b/qcom/anorak-rumi.dtsi
index 520cd2ef..aaf4ec69 100644
--- a/qcom/anorak-rumi.dtsi
+++ b/qcom/anorak-rumi.dtsi
@@ -189,3 +189,21 @@
 		<&gcc GCC_GPU_GPLL0_CLK_SRC>,
 		<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
 };
+
+&dispcc0 {
+	clocks = <&bi_tcxo>,
+		<&bi_tcxo_ao>,
+		<&sleep_clk>,
+		<&gcc GCC_DISP_AHB_CLK>;
+};
+
+&dispcc1 {
+	clocks = <&bi_tcxo>,
+		<&bi_tcxo_ao>,
+		<&sleep_clk>,
+		<&gcc GCC_DISP1_AHB_CLK>;
+};
+
+&debugcc {
+	clocks = <&bi_tcxo>;
+};
diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi
index 27c9b09c..ca06f731 100644
--- a/qcom/anorak.dtsi
+++ b/qcom/anorak.dtsi
@@ -326,7 +326,7 @@
 		reg = <0xaf20000 0x10000>;
 		reg-names = "drv-0";
 		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+		clocks = <&dispcc0 DISP_CC_MDSS_RSCC_AHB_CLK>;
 		qcom,tcs-offset = <0x1c00>;
 		qcom,drv-id = <0>;
 		qcom,tcs-config = <ACTIVE_TCS    0>,
@@ -347,7 +347,7 @@
 		reg = <0x15720000 0x10000>;
 		reg-names = "drv-0";
 		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+		clocks = <&dispcc1 DISP_CC_MDSS_RSCC_AHB_CLK>;
 		qcom,tcs-offset = <0x1c00>;
 		qcom,drv-id = <0>;
 		qcom,tcs-config = <ACTIVE_TCS    0>,
@@ -671,6 +671,31 @@
 		status = "ok";
 	};
 
+	apsscc: syscon@17aa0000 {
+		compatible = "syscon";
+		reg = <0x17aa0000 0x1c>;
+	};
+
+	mccc: syscon@190ba000 {
+		compatible = "syscon";
+		reg = <0x190ba000 0x54>;
+	};
+
+	debugcc: debug-clock-controller@0 {
+		compatible = "qcom,anorak-debugcc";
+		qcom,gcc = <&gcc>;
+		qcom,videocc = <&videocc>;
+		qcom,camcc = <&camcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,dispcc0 = <&dispcc0>;
+		qcom,dispcc1 = <&dispcc1>;
+		qcom,apsscc = <&apsscc>;
+		qcom,mccc = <&mccc>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo_clk_src";
+		#clock-cells = <1>;
+	};
+
 	rpmhcc: qcom,rpmhcc {
 		compatible = "qcom,dummycc";
 		clock-output-names = "rpmhcc_clocks";
@@ -695,9 +720,32 @@
 		#reset-cells = <1>;
 	};
 
-	dispcc: clock-controller@af00000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "dispcc_clocks";
+	dispcc0: clock-controller@af00000 {
+		compatible = "qcom,anorak-dispcc0", "syscon";
+		reg = <0xaf00000 0x20000>;
+		reg-name = "cc_base";
+		vdd_mm-supply = <&VDD_MM_LEVEL>;
+		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&rpmhcc RPMH_CXO_CLK_A>,
+			<&sleep_clk>,
+			<&gcc GCC_DISP_AHB_CLK>;
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc1: clock-controller@15700000 {
+		compatible = "qcom,anorak-dispcc1", "syscon";
+		reg = <0x15700000 0x20000>;
+		reg-name = "cc_base";
+		vdd_mm-supply = <&VDD_MM_LEVEL>;
+		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&rpmhcc RPMH_CXO_CLK_A>,
+			<&sleep_clk>,
+			<&gcc GCC_DISP1_AHB_CLK>;
+		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -1761,13 +1809,31 @@
 	status = "ok";
 };
 
-&disp_cc_mdss_core_gdsc {
-	compatible = "regulator-fixed";
+&disp0_cc_mdss_core_gdsc {
+	parent-supply = <&VDD_MM_LEVEL>;
+	clocks = <&gcc GCC_DISP_AHB_CLK>;
+	clock-names = "ahb_clk";
 	status = "ok";
 };
 
-&disp_cc_mdss_core_int2_gdsc {
-	compatible = "regulator-fixed";
+&disp0_cc_mdss_core_int2_gdsc {
+	parent-supply = <&VDD_MM_LEVEL>;
+	clocks = <&gcc GCC_DISP_AHB_CLK>;
+	clock-names = "ahb_clk";
+	status = "ok";
+};
+
+&disp1_cc_mdss_core_gdsc {
+	parent-supply = <&VDD_MM_LEVEL>;
+	clocks = <&gcc GCC_DISP1_AHB_CLK>;
+	clock-names = "ahb_clk";
+	status = "ok";
+};
+
+&disp1_cc_mdss_core_int2_gdsc {
+	parent-supply = <&VDD_MM_LEVEL>;
+	clocks = <&gcc GCC_DISP1_AHB_CLK>;
+	clock-names = "ahb_clk";
 	status = "ok";
 };
 
diff --git a/qcom/diwali-gdsc.dtsi b/qcom/diwali-gdsc.dtsi
index 48aa7a55..f4ced409 100644
--- a/qcom/diwali-gdsc.dtsi
+++ b/qcom/diwali-gdsc.dtsi
@@ -79,6 +79,48 @@
 		status = "disabled";
 	};
 
+	/* DISP_CC_0 GDSCs */
+	disp0_cc_mdss_core_gdsc: qcom,disp0-gdsc@af09000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf09000 0x4>;
+		regulator-name = "disp0_cc_mdss_core_gdsc";
+		proxy-supply = <&disp0_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	disp0_cc_mdss_core_int2_gdsc: qcom,disp0-gdsc@af0b000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf0b000 0x4>;
+		regulator-name = "disp0_cc_mdss_core_int2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	/* DISP_CC_1 GDSCs */
+	disp1_cc_mdss_core_gdsc: qcom,disp1-gdsc@15709000 {
+		compatible = "qcom,gdsc";
+		reg = <0x15709000 0x4>;
+		regulator-name = "disp1_cc_mdss_core_gdsc";
+		proxy-supply = <&disp1_cc_mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
+	disp1_cc_mdss_core_int2_gdsc: qcom,disp1-gdsc@1570b000 {
+		compatible = "qcom,gdsc";
+		reg = <0x1570b000 0x4>;
+		regulator-name = "disp1_cc_mdss_core_int2_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
 	gcc_apcs_gdsc_vote_ctrl: syscon@162128 {
 		compatible = "syscon";
 		reg = <0x162128 0x4>;