From ddb0ceb64b27e5e093047101e8b1a39736deb415 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Tue, 4 Feb 2020 04:34:05 -0800 Subject: [PATCH] ARM: dts: qcom: Update limit-rate and add limit-phy-submode on Lahaina Update limit-rate, 1 stands for Rate-A, 2 stands for Rate-B. In addition, add limit-phy-submode to select UFS PHY submode used for PHY calibration. Change-Id: Ifd0d55c0148256cd43d676b3b035c069ebb29fe2 --- bindings/ufs/ufs-qcom.txt | 5 ++++- qcom/lahaina-rumi.dtsi | 2 +- qcom/lahaina.dtsi | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index 0bb14521..c2c57c0a 100644 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -35,7 +35,10 @@ Optional properties: - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply - resets : specifies the PHY reset in the UFS controller - limit-rate : specifies if the rate has to be limited to A or B. - 1 = rate B, 0 = rate A. + 1 = rate A, 2 = rate B. +- limit-phy-submode : specifies the PHY submode which is used for PHY calibration, + 0 = non-G4, 1 = G4. + Example: ufsphy1: ufsphy@fc597000 { diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi index 43cf3c9a..b9f16682 100644 --- a/qcom/lahaina-rumi.dtsi +++ b/qcom/lahaina-rumi.dtsi @@ -27,7 +27,7 @@ &ufshc_mem { limit-tx-hs-gear = <1>; limit-rx-hs-gear = <1>; - limit-rate = <1>; + limit-rate = <2>; /* HS Rate-B */ vdd-hba-supply = <&gcc_ufs_phy_gdsc>; vdd-hba-fixed-regulator; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 24339c2d..7aa5aeab 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -1411,6 +1411,7 @@ phys = <&ufsphy_mem>; phy-names = "ufsphy"; lanes-per-direction = <2>; + limit-rate = <1>; /* HS Rate-A */ dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names =