From e34f3a8bbc0988208fa044848aef373949799fcc Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Thu, 27 Jan 2022 11:23:22 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Add proper name for eUSB2 PHY base address This change adds proper name for eUSB2 PHY register base address. Change-Id: Ia271a480c2abe452ac457ba1986867056608bed9 --- qcom/cape-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/cape-usb.dtsi b/qcom/cape-usb.dtsi index 0f8e8761..d70e50cc 100644 --- a/qcom/cape-usb.dtsi +++ b/qcom/cape-usb.dtsi @@ -81,7 +81,7 @@ reg = <0x88e3000 0x154>, <0x088e2000 0x4>, <0x0C276000 0x4>; - reg-names = "hsusb_phy_base", + reg-names = "eusb2_phy_base", "eud_enable_reg", "eud_detect_reg"; From 546981d265a32b8a25bdf79b8bb6dcf5bb708239 Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Thu, 27 Jan 2022 12:06:26 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add eUSB2 repeater reset GPIO configuration on Cape eUSB2 repeater is brought out of reset with PMIC GPIO 7. This change adds PMIC GPIO 7 configuration for using this GPIO. Also add PMIC GPIO 7 specific interrupt property which allows to receive related interrupt. Change-Id: Ibb8a8cfa257ef22f1590568d94c1078c5dae6369 --- qcom/cape-atp.dtsi | 7 ++++++- qcom/cape-cdp.dtsi | 7 ++++++- qcom/cape-mtp.dtsi | 7 ++++++- qcom/cape-pmic-overlay.dtsi | 12 ++++++++++++ qcom/cape-qrd.dtsi | 7 ++++++- 5 files changed, 36 insertions(+), 4 deletions(-) diff --git a/qcom/cape-atp.dtsi b/qcom/cape-atp.dtsi index 17cb9ecb..ccc9b591 100644 --- a/qcom/cape-atp.dtsi +++ b/qcom/cape-atp.dtsi @@ -109,7 +109,12 @@ reg = <0x3e>; vdd18-supply = <&S10B>; vdd3-supply = <&L2B>; - reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_LOW>; + reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&eusb2_reset_ctrl_default>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0x8e 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eusb2_rptr_reset_gpio_irq"; }; }; diff --git a/qcom/cape-cdp.dtsi b/qcom/cape-cdp.dtsi index 8c81c34b..8ed74b24 100644 --- a/qcom/cape-cdp.dtsi +++ b/qcom/cape-cdp.dtsi @@ -149,7 +149,12 @@ reg = <0x3e>; vdd18-supply = <&S10B>; vdd3-supply = <&L2B>; - reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_LOW>; + reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&eusb2_reset_ctrl_default>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0x8e 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eusb2_rptr_reset_gpio_irq"; }; }; diff --git a/qcom/cape-mtp.dtsi b/qcom/cape-mtp.dtsi index 94df59a7..aaefdf3e 100644 --- a/qcom/cape-mtp.dtsi +++ b/qcom/cape-mtp.dtsi @@ -153,7 +153,12 @@ reg = <0x4f>; vdd18-supply = <&S10B>; vdd3-supply = <&L2B>; - reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_LOW>; + reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&eusb2_reset_ctrl_default>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0x8e 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eusb2_rptr_reset_gpio_irq"; }; }; diff --git a/qcom/cape-pmic-overlay.dtsi b/qcom/cape-pmic-overlay.dtsi index cc54fcb1..9e01402d 100644 --- a/qcom/cape-pmic-overlay.dtsi +++ b/qcom/cape-pmic-overlay.dtsi @@ -64,6 +64,18 @@ qcom,drive-strength = <2>; }; }; + + eusb2_reset_ctrl { + eusb2_reset_ctrl_default: eusb2_reset_ctrl_default { + pins = "gpio7"; + function = "normal"; + input-enable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; }; &pmk8350_sdam_2 { diff --git a/qcom/cape-qrd.dtsi b/qcom/cape-qrd.dtsi index 04fbc0a7..39f5236c 100644 --- a/qcom/cape-qrd.dtsi +++ b/qcom/cape-qrd.dtsi @@ -207,7 +207,12 @@ reg = <0x4f>; vdd18-supply = <&S10B>; vdd3-supply = <&L2B>; - reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_LOW>; + reset-gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&eusb2_reset_ctrl_default>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0x8e 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eusb2_rptr_reset_gpio_irq"; }; };