From e001a217d03802916f829eaf6573e6c722a6aed1 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 23 Feb 2022 16:24:23 +0800 Subject: [PATCH] ARM: dts: msm: add dma-coherent option for etr1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dma-coherent option for etr1 on diwali and waipio to fix dma_sync_for_single_cpu() issue, which cause by a upstream change "Speed up for bounce buffer in flat mode". this change uses “dma_alloc_noncoherent + cache sync” to replace dma_alloc_coherent, These APIs only work with contiguous memory. since etr support iommu, etr buffer physical address is not contiguous. Change-Id: Ib179a65c49e893cc3a77d7accfeb6515e0d02e23 --- qcom/diwali-coresight.dtsi | 1 + qcom/waipio-coresight.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/diwali-coresight.dtsi b/qcom/diwali-coresight.dtsi index 7a573f83..9361948f 100644 --- a/qcom/diwali-coresight.dtsi +++ b/qcom/diwali-coresight.dtsi @@ -3088,6 +3088,7 @@ iommus = <&apps_smmu 0x0500 0>; qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + dma-coherent; coresight-csr = <&csr>; csr-atid-offset = <0x104>; diff --git a/qcom/waipio-coresight.dtsi b/qcom/waipio-coresight.dtsi index 3cead1e0..64a09bac 100644 --- a/qcom/waipio-coresight.dtsi +++ b/qcom/waipio-coresight.dtsi @@ -3336,6 +3336,7 @@ iommus = <&apps_smmu 0x0620 0>; qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + dma-coherent; coresight-csr = <&csr>; csr-atid-offset = <0x104>;