From 3f78604d85b25fbaba09104de3b008403d5920c4 Mon Sep 17 00:00:00 2001
From: Anvisha <anvisriv@qti.qualcomm.com>
Date: Fri, 25 Feb 2022 11:10:46 +0530
Subject: [PATCH] ARM: dts: msm: Enable qcedev, qrng and avb on parrot

This change adds dts entries for qcedev, qrng
and avb on parrot target.

Test: Nominal, Repeatitive and Adversial for qcedev and qrng.
      OrangeState_Unlcoked Test Case for AVB.

Change-Id: I0fc4e93755a4f585236aac0ef37edc2f9469e9fc
---
 qcom/parrot.dtsi | 55 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi
index b4fc3429..2828e4b3 100644
--- a/qcom/parrot.dtsi
+++ b/qcom/parrot.dtsi
@@ -318,6 +318,11 @@
 
 	android {
 		compatible = "android,firmware";
+		vbmeta {
+			compatible = "android,vbmeta";
+			parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+		};
+
 		fstab {
 			compatible = "android,fstab";
 			vendor {
@@ -325,7 +330,7 @@
 				dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
 				type = "ext4";
 				mnt_flags = "ro,barrier=1,discard";
-				fsmgr_flags = "wait,slotselect";
+				fsmgr_flags = "wait,slotselect,avb";
 				status = "ok";
 			};
 		};
@@ -1277,6 +1282,54 @@
 		status = "disabled";
 	};
 
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0484 0x0011>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+
+		qcom_cedev_ns_cb {
+		compatible = "qcom,qcedev,context-bank";
+		label = "ns_context";
+		iommus = <&apps_smmu 0x488 0x0>,
+			<&apps_smmu 0x49A 0x0>,
+			<&apps_smmu 0x49F 0x0>,
+			<&apps_smmu 0x498 0x5>;
+		dma-coherent;
+		};
+
+		qcom_cedev_s_cb {
+		compatible = "qcom,qcedev,context-bank";
+		label = "secure_context";
+		iommus = <&apps_smmu 0x492 0x0>,
+			<&apps_smmu 0x497 0x0>,
+			<&apps_smmu 0x49B 0x0>,
+			<&apps_smmu 0x49E 0x0>;
+		qcom,iommu-vmid = <0x9>;
+		qcom,secure-context-bank;
+		};
+	};
+
+	qcom_rng: qrng@10c3000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x10c3000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,no-clock-support;
+	};
+
 	ufsphy_mem: ufsphy_mem@1d87000 {
 		reg = <0x1d87000 0xe10>;
 		reg-names = "phy_mem";