diff --git a/qcom/neo-pinctrl.dtsi b/qcom/neo-pinctrl.dtsi
index a7631794..6f375f64 100644
--- a/qcom/neo-pinctrl.dtsi
+++ b/qcom/neo-pinctrl.dtsi
@@ -866,13 +866,13 @@
 			qupv3_se3_spi_active: qupv3_se3_spi_active {
 				mux {
 					pins = "gpio16", "gpio17",
-							"gpio18", "gpio19";
+							"gpio18";
 					function = "qup0_se3";
 				};
 
 				config {
 					pins = "gpio16", "gpio17",
-							"gpio18", "gpio19";
+							"gpio18";
 					drive-strength = <6>;
 					bias-disable;
 				};
@@ -881,17 +881,44 @@
 			qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
 				mux {
 					pins = "gpio16", "gpio17",
-							"gpio18", "gpio19";
+							"gpio18";
 					function = "gpio";
 				};
 
 				config {
 					pins = "gpio16", "gpio17",
-							"gpio18", "gpio19";
+							"gpio18";
 					drive-strength = <6>;
 					bias-disable;
 				};
 			};
+
+			qupv3_se3_spi_cs0_active: qupv3_se3_spi_cs0_active {
+				mux {
+					pins = "gpio19";
+					function = "qup0_se3";
+				};
+
+				config {
+					pins = "gpio19";
+					drive-strength = <6>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se3_spi_cs0_sleep: qupv3_se3_spi_cs0_sleep {
+				mux {
+					pins = "gpio19";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio19";
+					drive-strength = <6>;
+					/* Helios specific CS requirement. */
+					bias-pull-up;
+				};
+			};
 		};
 
 		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
diff --git a/qcom/neo-qupv3.dtsi b/qcom/neo-qupv3.dtsi
index f16de479..c4a9ac7a 100644
--- a/qcom/neo-qupv3.dtsi
+++ b/qcom/neo-qupv3.dtsi
@@ -220,8 +220,8 @@
 			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&qupv3_se3_spi_active>;
-		pinctrl-1 = <&qupv3_se3_spi_sleep>;
+		pinctrl-0 = <&qupv3_se3_spi_active>, <&qupv3_se3_spi_cs0_active>;
+		pinctrl-1 = <&qupv3_se3_spi_sleep>, <&qupv3_se3_spi_cs0_sleep>;
 		dmas = <&gpi_dma0 0 3 1 64 0>,
 			<&gpi_dma0 1 3 1 64 0>;
 		dma-names = "tx", "rx";