From ee8f170d51e5e9bbc15c37d8c00f8184332fbb9d Mon Sep 17 00:00:00 2001 From: smaniar Date: Sun, 17 Oct 2021 01:37:28 +0530 Subject: [PATCH] ARM: dts: msm: Enabled IPCC_Compute_L0 & IPCLite protocol These changes enable IPCLite communication protocol and IPCC_Compute_L0 interrupt of IPCC HW controller. IPCLite protocol relies on IPCC Compute_l0 interrupt for its inter-proc signalling. Change-Id: Ic4865e6e0e216f1f0aa75fe44bb89904cc989fd5 --- bindings/soc/qcom/qcom,ipclite.txt | 79 ++++++++++++ qcom/waipio.dtsi | 198 +++++++++++++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 bindings/soc/qcom/qcom,ipclite.txt diff --git a/bindings/soc/qcom/qcom,ipclite.txt b/bindings/soc/qcom/qcom,ipclite.txt new file mode 100644 index 00000000..027d5dc5 --- /dev/null +++ b/bindings/soc/qcom/qcom,ipclite.txt @@ -0,0 +1,79 @@ +Qualcomm Technologies, Inc. IPCLite Framework + +This binding describes IPCLite protocol within the system. +IPCLite is a light weight mechanism for communication between +subsystem-pairs. This protocol will be primarily used to +support low-latency signalling for Global Synx framework. + +- compatible : + Usage: required + Value type: + Definition: must be "qcom,ipclite" + +- label: + Usage: optional + Value type: + Definition: should specify the subsystem name this edge corresponds to. + +- interrupts: + Usage: required + Value type: + Definition: should specify the IRQ used by the remote processor to + signal this processor about communication related events + +- qcom,remote-pid: + Usage: required for ipcmem + Value type: + Definition: specifies the identifier of the remote endpoint of this edge + +- mboxes: + Usage: required + Value type: + Definition: reference to the "rpm_hlos" mailbox in APCS, as described + in mailbox/mailbox.txt + += EXAMPLE +The following example represents the IPCLite node along with cdsp sub-node. + +ipclite { + compatible = "qcom,ipclite"; + memory-region = <&global_sync_mem>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ipclite_cdsp: cdsp { + qcom,remote-pid = <5>; + label = "cdsp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; +}; diff --git a/qcom/waipio.dtsi b/qcom/waipio.dtsi index c1415ab4..3af7fdb8 100644 --- a/qcom/waipio.dtsi +++ b/qcom/waipio.dtsi @@ -1559,6 +1559,204 @@ #mbox-cells = <2>; }; + ipcc_compute_l0: qcom,ipcc_compute_l0@408000 { + compatible = "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipclite { + compatible = "qcom,ipclite"; + memory-region = <&global_sync_mem>; + hwlocks = <&tcsr_mutex 11>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ipclite_apss: apss { + qcom,remote-pid = <0>; + label = "apss"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cdsp: cdsp { + qcom,remote-pid = <5>; + label = "cdsp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_cvp: cvp { + qcom,remote-pid = <6>; + label = "cvp"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + + ipclite_vpu: vpu { + qcom,remote-pid = <8>; + label = "vpu"; + + ipclite_signal_0 { + index = <0>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_1 { + index = <1>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_2 { + index = <2>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + + ipclite_signal_3 { + index = <3>; + mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU + IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>; + interrupt-parent = <&ipcc_compute_l0>; + interrupts = ; + }; + }; + }; + tcsr: syscon@1fc0000 { compatible = "syscon"; reg = <0x1fc0000 0x30000>;