From 624a995c1f8c251f28fb513312691e12d81c7a8f Mon Sep 17 00:00:00 2001
From: Kalpak Kawadkar <kkawadka@qti.qualcomm.com>
Date: Wed, 11 May 2022 21:26:46 +0530
Subject: [PATCH] ARM: dts: msm: Add support for dummy clocks/GDSC for Ravelin

Add the clock & GDSC's handles for clients to be able
to request on them for RAVELIN.

Change-Id: I9693584f85c5a6d49fe90b721c4a0279c841cd0c
---
 qcom/diwali-gdsc.dtsi |  17 +++++
 qcom/ravelin.dtsi     | 172 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 189 insertions(+)

diff --git a/qcom/diwali-gdsc.dtsi b/qcom/diwali-gdsc.dtsi
index 9c3d31d3..48aa7a55 100644
--- a/qcom/diwali-gdsc.dtsi
+++ b/qcom/diwali-gdsc.dtsi
@@ -170,6 +170,23 @@
 		status = "disabled";
 	};
 
+	gcc_venus_gdsc: qcom,gdsc@1b6020 {
+		compatible = "qcom,gdsc";
+		reg = <0x1b6020 0x4>;
+		regulator-name = "gcc_venus_gdsc";
+		qcom,retain-regs;
+		status = "disabled";
+	};
+
+	gcc_vcodec0_gdsc: qcom,gdsc@1b6044 {
+		compatible = "qcom,gdsc";
+		reg = <0x1b6044 0x4>;
+		regulator-name = "gcc_vcodec0_gdsc";
+		qcom,retain-regs;
+		qcom,support-hw-trigger;
+		status = "disabled";
+	};
+
 	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@18d050 {
 		compatible = "qcom,gdsc";
 		reg = <0x18d050 0x4>;
diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi
index 2ac25550..e643924f 100644
--- a/qcom/ravelin.dtsi
+++ b/qcom/ravelin.dtsi
@@ -1,4 +1,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,camcc-ravelin.h>
+#include <dt-bindings/clock/qcom,dispcc-ravelin.h>
+#include <dt-bindings/clock/qcom,gcc-ravelin.h>
+#include <dt-bindings/clock/qcom,gpucc-ravelin.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Ravelin";
@@ -324,7 +329,174 @@
 		#mbox-cells = <2>;
 	};
 
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+
+		pcie_0_pipe_clk: pcie_0_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "pcie_0_pipe_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_rx_symbol_0_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_rx_symbol_1_clk";
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "ufs_phy_tx_symbol_0_clk";
+			#clock-cells = <0>;
+		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	bi_tcxo: bi_tcxo {
+		compatible = "fixed-factor-clock";
+		clock-mult = <1>;
+		clock-div = <4>;
+		clocks = <&xo_board>;
+		#clock-cells = <0>;
+	};
+
+	bi_tcxo_ao: bi_tcxo_ao {
+		compatible = "fixed-factor-clock";
+		clock-mult = <1>;
+		clock-div = <4>;
+		clocks = <&xo_board>;
+		#clock-cells = <0>;
+	};
+
+	camcc: clock-controller@ade0000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "camcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "dispcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gcc: clock-controller@100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@3d90000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gpucc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	rpmhcc: qcom,rpmhcc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "rmphcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
 };
 
 #include "ravelin-pinctrl.dtsi"
+#include "diwali-gdsc.dtsi"
 
+&gcc_pcie_0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_vcodec0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gcc_venus_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&cam_cc_camss_top_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&disp_cc_mdss_core_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&disp_cc_mdss_core_int2_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gpu_cc_cx_gdsc {
+	compatible = "regulator-fixed";
+	status = "ok";
+};
+
+&gpu_cc_gx_gdsc {
+	compatible = "regulator-fixed";
+	sw-reset = <&gpu_cc_gx_sw_reset>;
+	status = "ok";
+};