diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt
index c5eb6694..513ffe16 100644
--- a/bindings/clock/qcom,camcc.txt
+++ b/bindings/clock/qcom,camcc.txt
@@ -1,14 +1,20 @@
-Qualcomm Camera Clock & Reset Controller Binding
-------------------------------------------------
+Qualcomm Technologies, Inc. Camera Clock & Reset Controller Binding
+-------------------------------------------------------------------
 
 Required properties :
-- compatible : shall contain "qcom,sdm845-camcc".
+- compatible : shall contain "qcom,sdm845-camcc" or "qcom,lahaina-camcc".
 - reg : shall contain base register location and length.
+- reg-names: names of registers listed in the same order as in
+		the reg property.
+- vdd_<rail>-supply: The logic rail supply.
+- clock-names: Shall contain "cfg_ahb_clk"
+- clocks: phandle + clock reference to the GCC AHB clock.
 - #clock-cells : from common clock binding, shall contain 1.
 - #reset-cells : from common reset binding, shall contain 1.
 - #power-domain-cells : from generic power domain binding, shall contain 1.
 
 Example:
+1.
 	camcc: clock-controller@ad00000 {
 		compatible = "qcom,sdm845-camcc";
 		reg = <0xad00000 0x10000>;
@@ -16,3 +22,16 @@ Example:
 		#reset-cells = <1>;
 		#power-domain-cells = <1>;
 	};
+2.
+	clock_camcc: qcom,camcc@ad00000 {
+		compatible = "qcom,camcc-kona";
+		reg = <0xad00000 0x10000>;
+		reg-names = "cc_base";
+		vdd_mm-supply = <&VDD_MM_LEVEL>;
+		vdd_mx-supply = <&VDD_MXA_LEVEL>;
+		clock-names = "cfg_ahb_clk";
+		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		#power-domain-cells = <1>;
+	};