From f62264a76bd03d2e1801b90e4b3789c1fef99e16 Mon Sep 17 00:00:00 2001
From: Mao Jinlong <jinlmao@qti.qualcomm.com>
Date: Thu, 2 Apr 2020 20:44:24 +0800
Subject: [PATCH] ARM: dts: msm: Disable tpdm ddr for lahaina

Disable tpdm ddr to avoid register access issue.

Change-Id: Ie7a0922f3d7b09d2c75005d5393576dd424a0e2a
---
 qcom/lahaina-coresight.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi
index 328d161f..585b0419 100644
--- a/qcom/lahaina-coresight.dtsi
+++ b/qcom/lahaina-coresight.dtsi
@@ -2433,6 +2433,7 @@
 		clocks = <&clock_aop QDSS_CLK>;
 		clock-names = "apb_pclk";
 
+		status = "disabled";
 		qcom,msr-fix-req;
 
 		out-ports {