From f794bd404b57bdbbb38ab59116e21c93813561bb Mon Sep 17 00:00:00 2001
From: Mukesh Kumar Savaliya <msavaliy@qti.qualcomm.com>
Date: Fri, 5 Mar 2021 20:18:14 +0530
Subject: [PATCH] ARM: dts: msm: Configure RX sleep state with GPIO mode for
 wakeup

This change configures sleep state of UART RX line into GPIO mode to
support the wakeup feature. Pinctrl driver and wakeup functionality
expects PIN to be in gpio mode.

Change-Id: If4133645023050bf93b96ba8c358baa1ef87f3e6
---
 qcom/waipio-pinctrl.dtsi | 33 ++++++++++++++++++++++++++++++---
 qcom/waipio-qupv3.dtsi   |  8 ++++----
 2 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/qcom/waipio-pinctrl.dtsi b/qcom/waipio-pinctrl.dtsi
index 84c1facf..c3ba9fbe 100644
--- a/qcom/waipio-pinctrl.dtsi
+++ b/qcom/waipio-pinctrl.dtsi
@@ -1396,14 +1396,14 @@
 			};
 		};
 
-		qupv3_se20_ctsrx: qupv3_se20_ctsrx {
+		qupv3_se20_cts: qupv3_se20_cts {
 			mux {
-				pins = "gpio76", "gpio79";
+				pins = "gpio76";
 				function = "qup20";
 			};
 
 			config {
-				pins = "gpio76", "gpio79";
+				pins = "gpio76";
 				drive-strength = <2>;
 				bias-disable;
 			};
@@ -1434,6 +1434,33 @@
 				bias-pull-up;
 			};
 		};
+
+		/* RX to be in gpio mode for sleep config */
+		qupv3_se20_rx_wake: qupv3_se20_rx_wake {
+			mux {
+				pins = "gpio79";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio79";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_rx_active: qupv3_se20_rx_active {
+			mux {
+				pins = "gpio79";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio79";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
 	};
 
 	nfc {
diff --git a/qcom/waipio-qupv3.dtsi b/qcom/waipio-qupv3.dtsi
index 6c84dd39..998c4d05 100644
--- a/qcom/waipio-qupv3.dtsi
+++ b/qcom/waipio-qupv3.dtsi
@@ -1069,10 +1069,10 @@
 		pinctrl-names = "default", "active", "sleep";
 		pinctrl-0 = <&qupv3_se20_default_cts>,
 			<&qupv3_se20_default_rtsrx>, <&qupv3_se20_default_tx>;
-		pinctrl-1 = <&qupv3_se20_ctsrx>, <&qupv3_se20_rts>,
-						<&qupv3_se20_tx>;
-		pinctrl-2 = <&qupv3_se20_ctsrx>, <&qupv3_se20_rts>,
-						<&qupv3_se20_tx>;
+		pinctrl-1 = <&qupv3_se20_cts>, <&qupv3_se20_rts>,
+			<&qupv3_se20_tx>, <&qupv3_se20_rx_active>;
+		pinctrl-2 = <&qupv3_se20_cts>, <&qupv3_se20_rts>,
+			<&qupv3_se20_tx>, <&qupv3_se20_rx_wake>;
 		qcom,wakeup-byte = <0xFD>;
 		qcom,wrapper-core = <&qupv3_2>;
 		status = "disabled";