From f7a6087e7febfeeed06b37e9962a142a8d40aea5 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Mon, 8 May 2023 16:25:24 +0530 Subject: [PATCH] ARM: dts: msm: Fix the frequency to clock mismatch on anorak Fix the frequency to clock mapping on the anorak. Change-Id: I1f2e3d0d5b4894685940ff289e8e35e7365813b0 --- qcom/anorak-pcie.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/anorak-pcie.dtsi b/qcom/anorak-pcie.dtsi index 02065c03..64383d8b 100644 --- a/qcom/anorak-pcie.dtsi +++ b/qcom/anorak-pcie.dtsi @@ -101,9 +101,9 @@ "pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk", "pcie_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src"; - max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <100000000>, <0>, - <0>, <0>, <0>, <0>, <0>, <0>; + max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <100000000>, + <0>, <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_PHY_BCR>; @@ -367,9 +367,9 @@ "pcie_aggre_noc_0_axi_clk", "pcie_aggre_noc_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_pipe_clk_mux", "pcie_1_pipe_div2_clk", "pcie_pipe_clk_ext_src"; - max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <100000000>, <0>, - <0>, <0>, <0>, <0>, <0>; + max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <100000000>, + <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_PHY_BCR>; @@ -638,9 +638,9 @@ "pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_pipe_clk_mux", "pcie_phy_aux_clk_mux", "pcie_2_pipe_div2_clk", "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk_ext_src"; - max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <100000000>, <0>, - <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <100000000>, + <0>, <0>, <0>, <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_2_BCR>, <&gcc GCC_PCIE_2_PHY_BCR>;