From fb7773e1a8e67f73ad7d8db71a5c1ab2f2437324 Mon Sep 17 00:00:00 2001
From: Raghavendra Rao Ananta <rananta@quicinc.com>
Date: Fri, 7 Jun 2019 10:59:50 -0700
Subject: [PATCH] ARM: dts: msm: Add pinctrl node for TLMM on Lahaina SoC

Add pinctrl node with compatiability of qcom,lahaina-pinctrl,
to enable Top Level Mode Multiplexer block(TLMM) on Lahaina SoC.

Change-Id: Iac61248547061d5cb2ec42e442117f676f54ff77
---
 qcom/lahaina-pinctrl.dtsi | 11 +++++++++++
 qcom/lahaina.dtsi         |  2 ++
 2 files changed, 13 insertions(+)
 create mode 100644 qcom/lahaina-pinctrl.dtsi

diff --git a/qcom/lahaina-pinctrl.dtsi b/qcom/lahaina-pinctrl.dtsi
new file mode 100644
index 00000000..4870340f
--- /dev/null
+++ b/qcom/lahaina-pinctrl.dtsi
@@ -0,0 +1,11 @@
+&soc {
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,lahaina-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 35ec6430..709b4219 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -284,3 +284,5 @@
 		};
 	};
 };
+
+#include "lahaina-pinctrl.dtsi"