From fc3ec1c07ca0c13b91305a502bf168437310ef1e Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 16 Sep 2022 00:09:58 +0530 Subject: [PATCH] ARM: dts: msm: Add support for Ravelin GPU Add the necessary DT nodes to support GPU in Ravelin. Change-Id: I5e19f54dcb4a193250dc26bb3e4792f15432d235 --- qcom/ravelin-gpu.dtsi | 277 ++++++++++++++++++++++++++++++++++++++++++ qcom/ravelin.dtsi | 1 + 2 files changed, 278 insertions(+) create mode 100644 qcom/ravelin-gpu.dtsi diff --git a/qcom/ravelin-gpu.dtsi b/qcom/ravelin-gpu.dtsi new file mode 100644 index 00000000..99c3f425 --- /dev/null +++ b/qcom/ravelin-gpu.dtsi @@ -0,0 +1,277 @@ + +#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) + +&soc { + msm_gpu: qcom,kgsl-3d0@3d00000 { + compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-gen6-3-26-0"; + status = "ok"; + + reg = <0x3d00000 0x40000>, <0x03d61000 0x800>, + <0x03d7d000 0x1D000>, <0x03d9e000 0x1000>, + <0x10900000 0x80000>; + + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "gmu_wrapper", + "cx_misc", "qdss_gfx"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&aoss_qmp>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + + clock-names = "core_clk", + "gmu_clk", + "mem_clk", + "mem_iface_clk", + "hub_cx_int_clk", + "smmu_vote", + "apb_pclk", + "gpu_cc_cx_gmu", + "gpu_cc_hub_cx_int", + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + + regulator-names = "vddcx", "vdd"; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + vdd-supply = <&gpu_cc_gx_gdsc>; + + qcom,chipid = <0x06010300>; + qcom,gpu-model = "Adreno613v1"; + + qcom,no-nap; + + qcom,min-access-length = <32>; + qcom,ubwc-mode = <2>; + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + + qcom,tzone-names = "gpuss"; + + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gpu_icc_path"; + + qcom,bus-table-ddr7 = + , /* index=0 */ + , /* index=1 LOW_SVS */ + , /* index=2 LOW_SVS */ + , /* index=3 SVS */ + , /* index=4 SVS */ + , /* index=5 SVS_L1 */ + , /* index=6 NOM */ + , /* index=7 NOM */ + ; /* index=8 TURBO */ + + qcom,bus-table-ddr8 = + , /* index=0 */ + , /* index=1 LOW_SVS */ + , /* index=2 LOW_SVS */ + , /* index=3 LOW_SVS */ + , /* index=4 SVS */ + , /* index=5 SVS */ + , /* index=6 SVS */ + , /* index=7 SVS_L1 */ + , /* index=8 NOM */ + , /* index=9 TURBO */ + ; /* index=10 TURBO */ + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 128K Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <131072>; + qcom,mempool-reserved = <128>; + }; + /* 256K Page Pool configuration */ + qcom,gpu-mempool@4 { + reg = <4>; + qcom,mempool-page-size = <262144>; + qcom,mempool-reserved = <80>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@5 { + reg = <5>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <5>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1010000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <8>; + + qcom,bus-freq-ddr8 = <10>; + qcom,bus-min-ddr8 = <10>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <955000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <8>; + qcom,bus-max-ddr7 = <8>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <9>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <850000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <8>; + qcom,bus-min-ddr7 = <7>; + qcom,bus-max-ddr7 = <8>; + + qcom,bus-freq-ddr8 = <9>; + qcom,bus-min-ddr8 = <8>; + qcom,bus-max-ddr8 = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <765000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <8>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <7>; + qcom,bus-max-ddr8 = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <605000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <5>; + qcom,bus-min-ddr7 = <4>; + qcom,bus-max-ddr7 = <7>; + + qcom,bus-freq-ddr8 = <7>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <8>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <500000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <4>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <5>; + + qcom,bus-freq-ddr8 = <6>; + qcom,bus-min-ddr8 = <5>; + qcom,bus-max-ddr8 = <7>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <340000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <2>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <4>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <3>; + qcom,bus-max-ddr8 = <6>; + }; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x03da0000 0x40000>; + + vddcx-supply = <&gpu_cc_cx_gdsc>; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x0 0x400>; + qcom,iommu-dma = "disabled"; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 0x2 0x400>; + qcom,iommu-dma = "disabled"; + }; + }; + +}; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 94ed640d..ffefaf02 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -327,6 +327,7 @@ }; #include "msm-arm-smmu-ravelin.dtsi" +#include "ravelin-gpu.dtsi" #include "ravelin-dma-heaps.dtsi" #include "ravelin-reserved-memory.dtsi" #include "ravelin-dma-heaps.dtsi"