From f61207eab0c1d07f4109a52a11cc38e7487481d1 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Fri, 11 Nov 2022 14:51:10 +0800 Subject: [PATCH 1/2] ARM: dts: msm: Add initial DCVS devices for ravelin Add initial set of DCVS device nodes for ravelin. This includes the QCOM DCVS devices, PMU device nodes, memlat device nodes and mapping tables, and bwmon device nodes. Change-Id: I47853c1bd2771b236d416fa38b087e58107eca46 --- qcom/ravelin.dtsi | 336 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 1285b084..1391aa91 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -47,6 +47,19 @@ mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; + sram: sram@17D09100 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09100 0x0 0x200>; + ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scp-shmem"; + reg = <0x0 0x0 0x0 0x200>; + }; + }; + firmware: firmware {}; cpus { @@ -646,6 +659,51 @@ }; }; + rimps: qcom,rimps@17400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,rimps"; + reg = <0x17400000 0x10>, + <0x17d90000 0x2000>; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&rimps 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_pmu: protocol@86 { + reg = <0x86>; + #clock-cells = <1>; + }; + + scmi_plh: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; + + scmi_cpufreqstat: protocol@84 { + reg = <0x84>; + #clock-cells = <1>; + }; + + scmi_shared_rail: protocol@88 { + reg = <0x88>; + #clock-cells = <1>; + }; + }; + + rimps_log: qcom,rimps_log@17d09c00 { + compatible = "qcom,rimps-log"; + reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>; + mboxes = <&rimps 1>; + }; + qcom,secure-buffer { compatible = "qcom,secure-buffer"; qcom,vmid-cp-camera-preview-ro; @@ -1125,6 +1183,284 @@ }; }; + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + reg = < 0x17D09300 0x300>; + reg-names = "pmu-base"; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0xFF 0x02 >, + < 0x0011 0xFF 0xFF 0x00 >, + < 0x0017 0xFF 0xFF 0xFF >, + < 0x002A 0xFF 0xFF 0xFF >, + < 0x4005 0xF0 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + ddr4 { + qcom,ddr-type = <7>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1017000 >, + < 1353600 >, + < 1555000 >, + < 1708000 >, + < 2092000 >; + }; + + ddr5 { + qcom,ddr-type = <8>; + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1555000 >, + < 1708000 >, + < 2092000 >, + < 2736000 >, + < 3196000 >; + }; + }; + + ddrqos_freq_table: ddrqos-freq-table { + qcom,freq-tbl = + < 0 >, + < 1 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0090>; + }; + }; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + + qcom_ddrqos_dcvs_hw: ddrqos { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <3>; + qcom,bus-width = <1>; + qcom,freq-tbl = <&ddrqos_freq_table>; + + ddrqos_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + qcom,be-stall-ev = <0x4005>; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1113600 547000 >, + < 1497600 768000 >, + < 1804800 1017000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1113600 547000 >, + < 1497600 768000 >, + < 1804800 1555000 >; + }; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1190400 1017000 >, + < 1497600 1353600 >, + < 1651200 1555000 >, + < 2112000 1708000 >, + < 2361600 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1651200 1555000 >, + < 1900800 1708000 >, + < 2112000 2092000 >, + < 2361600 3196000 >; + }; + }; + + silver-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1497600 547000 >, + < 1804800 768000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1497600 547000 >, + < 1804800 768000 >; + }; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 1900800 1555000 >, + < 2112000 1708000 >, + < 2361600 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1190400 547000 >, + < 1497600 768000 >, + < 1651200 1017000 >, + < 2054400 1555000 >, + < 2112000 1708000 >, + < 2361600 2092000 >; + }; + }; + + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpufreq-memfreq-tbl = + < 300000 307200 >, + < 691200 556800 >, + < 806400 652800 >, + < 940800 806400 >, + < 1113600 940800 >, + < 1324800 1056000 >, + < 1497600 1190400 >, + < 1651200 1248000 >, + < 1804800 1420800 >, + < 1958400 1440000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 300000 307200 >, + < 960000 556800 >, + < 1190400 806400 >, + < 1344000 940800 >, + < 1651200 1190400 >, + < 1900800 1382400 >, + < 2054400 1420800 >, + < 2361600 1440000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2054400 307200 >, + < 2361600 1420800 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + + }; + + ddrqos { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddrqos_dcvs_hw>; + qcom,sampling-path = <&ddrqos_dcvs_sp>; + qcom,miss-ev = <0x2A>; + + ddrqos_gold_lat: gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2300000 0 >, + < 3000000 1 >; + qcom,sampling-enabled; + }; + + }; + }; + + bwmon_ddr: qcom,bwmon-ddr@19091000 { + compatible = "qcom,bwmon5"; + reg = <0x19091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + }; + sdhc_1: sdhci@7C4000 { status = "disabled"; From 78a0464705d1a4c0f417b5e1ea5d08e1b5c143a9 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 14 Nov 2022 10:54:46 +0800 Subject: [PATCH 2/2] ARM: dts: msm: update memlat table for Ravelin Update memlat table for Ravelin. Change-Id: I85d07ae6c03c68270a7852d0b0f9d8319622b063 --- qcom/ravelin.dtsi | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 1391aa91..ede48c3a 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1393,16 +1393,15 @@ compatible = "qcom,memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; qcom,cpufreq-memfreq-tbl = - < 300000 307200 >, - < 691200 556800 >, + < 499200 307200 >, + < 672000 566400 >, < 806400 652800 >, - < 940800 806400 >, - < 1113600 940800 >, - < 1324800 1056000 >, - < 1497600 1190400 >, - < 1651200 1248000 >, - < 1804800 1420800 >, - < 1958400 1440000 >; + < 921600 825600 >, + < 1094400 940800 >, + < 1286400 1075200 >, + < 1478400 1209600 >, + < 1632000 1305600 >, + < 1804800 1440000 >; qcom,sampling-enabled; }; @@ -1410,14 +1409,14 @@ compatible = "qcom,memlat-mon"; qcom,cpulist = <&CPU6 &CPU7>; qcom,cpufreq-memfreq-tbl = - < 300000 307200 >, - < 960000 556800 >, - < 1190400 806400 >, + < 691200 307200 >, + < 960000 566400 >, + < 1190400 825600 >, < 1344000 940800 >, - < 1651200 1190400 >, - < 1900800 1382400 >, - < 2054400 1420800 >, - < 2361600 1440000 >; + < 1651200 1209600 >, + < 1900800 1305600 >, + < 2054400 1401600 >, + < 2208000 1440000 >; qcom,sampling-enabled; };