Files
kernel_xiaomi_sm8450-device…/qcom/neo-rumi.dtsi
Kalpak Kawadkar c314834286 ARM: dts: msm: Add support for RPMHCC clock controller on NEO
Add support for RPMHCC clock controller on NEO platform. While
at it, use dummy clock controller for RPMHCC on RUMI platform.

Change-Id: I63a09d13f066ccafe6be721293b5757a80da7e12
2022-03-01 19:01:38 +05:30

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#include <dt-bindings/clock/qcom,gcc-neo.h>
&soc {
timer {
clock-frequency = <5000000>;
};
timer@17420000 {
clock-frequency = <5000000>;
};
qcom,wdt@17410000 {
status = "disabled";
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb_emuphy: phy@A784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0A784000 0x9500>;
qcom,emu-init-seq = <0xfffff 0x4
0xffff3 0x4
0xffff0 0x4
0x00100000 0x20
0x00000000 0x20
0x000101F0 0x20
0x00100000 0x3c
0x00000000 0x3c
0x0010060 0x3c
0x0 0x4>;
};
disp_rsc: rsc@af20000 {
status = "nok";
};
bi_tcxo: bi_tcxo {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <2>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
bi_tcxo_ao: bi_tcxo_ao {
compatible = "fixed-factor-clock";
clock-mult = <1>;
clock-div = <2>;
clocks = <&xo_board>;
#clock-cells = <0>;
};
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L10A>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L7A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
max-frequency = <100000000>;
/delete-property/ mmc-ddr-1_8v;
/delete-property/ mmc-hs200-1_8v;
/delete-property/ mmc-hs400-1_8v;
/delete-property/ mmc-hs400-enhanced-strobe;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
};
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};
&videocc {
clocks = <&bi_tcxo>,
<&sleep_clk>,
<&gcc GCC_VIDEO_AHB_CLK>;
};
&gpucc {
clocks = <&bi_tcxo>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
};
&camcc {
clocks = <&bi_tcxo>, <&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
};
&qupv3_se11_2uart {
qcom,rumi_platform;
};
&dispcc {
clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
};
&tsens0 {
status = "disabled";
};
&debugcc {
clocks = <&bi_tcxo>;
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};
&rpmhcc {
compatible = "qcom,dummycc";
clock-output-names = "rpmhcc_clocks";
};