mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
03bb3be657
Add initial devicetree nodes and entries to support and enable PCIe root complex on sdxlemur. Change-Id: I6815e38a9fbe4f9517ea88e3fc85168a0cca9772
98 lines
1.6 KiB
Plaintext
98 lines
1.6 KiB
Plaintext
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&soc {
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sdxlemur-pinctrl";
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reg = <0xf100000 0x300000>;
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reg-names = "pinctrl";
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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uart3_console_active: uart3_console_active {
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mux {
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pins = "gpio8", "gpio9";
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function = "blsp_uart3";
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};
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config {
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pins = "gpio8", "gpio9";
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drive-strength = <2>;
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bias-disable;
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};
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};
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uart3_console_sleep: uart3_console_sleep {
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mux {
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pins = "gpio8", "gpio9";
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function = "blsp_uart3";
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};
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config {
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pins = "gpio8", "gpio9";
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drive-strength = <2>;
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bias-disable;
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};
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};
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pcie0 {
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pcie0_clkreq_default: pcie0_clkreq_default {
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mux {
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pins = "gpio56";
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function = "pcie_clkreq";
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};
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config {
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pins = "gpio56";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_perst_default: pcie0_perst_default {
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mux {
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pins = "gpio57";
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function = "gpio";
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};
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config {
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pins = "gpio57";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie0_wake_default: pcie0_wake_default {
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mux {
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pins = "gpio53";
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function = "gpio";
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};
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config {
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pins = "gpio53";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_clkreq_sleep: pcie0_clkreq_sleep {
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mux {
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pins = "gpio56";
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function = "gpio";
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};
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config {
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pins = "gpio56";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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};
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};
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