mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
4408340b6f
Fix typographical error to fix the compilation issue. Change-Id: I924d558e2916935c3c12ce751ec8fc5e07b2aa43
675 lines
14 KiB
Plaintext
675 lines
14 KiB
Plaintext
#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
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#include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,dcc_v2.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sdxlemur.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm Technologies, Inc. SDXLEMUR";
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compatible = "qcom,sdxlemur";
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qcom,msm-id = <458 0x10000>;
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interrupt-parent = <&intc>;
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aliases {
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pci-domain0 = &pcie0; /* PCIe0 domain */
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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reserved_memory: reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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cmd_db: reserved-memory@8fe20000 {
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compatible = "qcom,cmd-db";
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no-map;
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reg = <0x8fe20000 0x20000>;
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};
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mpss_adsp_mem: mpss_adsp_region@90800000 {
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no-map;
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reg = <0x90800000 0x10000000>;
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};
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tz_mem: tz_mem_region@8ff00000 {
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no-map;
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reg = <0x8ff00000 0x600000>;
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};
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smem_mem: smem_region@8fe40000 {
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no-map;
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reg = <0x8fe40000 0xc0000>;
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label = "smem_mem";
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};
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peripheral_mem: peripheral_region@8fd00000 {
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no-map;
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reg = <0x8fd00000 0x140000>;
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};
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/*
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* The exact size of this region may vary based on DDR size.
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* 0x100000 will be valid for all DDR sizes at the cost of
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* slightly reducing the memory available for HLOS.
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*/
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peripheral_mem2: peripheral_region2@8fb00000 {
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no-map;
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reg = <0x8fb00000 0x100000>;
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};
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mpss_dsm: mpss_dsm_region@8c400000 {
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no-map;
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reg = <0x8c400000 0x3200000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00000000 0xffffffff>;
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reusable;
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size = <0x400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00000000 0xffffffff>;
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reusable;
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alignment = <0x400000>;
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size = <0xC00000>;
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linux,cma-default;
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};
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};
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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enable-method = "psci";
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cpu-idle-states = <&A7_SPC &A7_PC &CX_MIN>;
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@17800000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x17800000 0x1000>,
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<0x17802000 0x1000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 12 0xf08>,
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<1 10 0xf08>,
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<1 11 0xf08>;
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clock-frequency = <19200000>;
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};
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timer@17820000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17820000 0x1000>;
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clock-frequency = <19200000>;
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frame@17821000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0x17821000 0x1000>,
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<0x17822000 0x1000>;
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};
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frame@17823000 {
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frame-number = <1>;
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interrupts = <0 8 0x4>;
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reg = <0x17823000 0x1000>;
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status = "disabled";
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};
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frame@17824000 {
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frame-number = <2>;
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interrupts = <0 9 0x4>;
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reg = <0x17824000 0x1000>;
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status = "disabled";
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};
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frame@17825000 {
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frame-number = <3>;
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interrupts = <0 10 0x4>;
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reg = <0x17825000 0x1000>;
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status = "disabled";
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};
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frame@17826000 {
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frame-number = <4>;
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interrupts = <0 11 0x4>;
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reg = <0x17826000 0x1000>;
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status = "disabled";
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};
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frame@17827000 {
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frame-number = <5>;
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interrupts = <0 12 0x4>;
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reg = <0x17827000 0x1000>;
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status = "disabled";
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};
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frame@17828000 {
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frame-number = <6>;
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interrupts = <0 13 0x4>;
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reg = <0x17828000 0x1000>;
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status = "disabled";
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};
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frame@17829000 {
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frame-number = <7>;
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interrupts = <0 14 0x4>;
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reg = <0x17829000 0x1000>;
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status = "disabled";
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};
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};
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restart_pshold: restart@c264000 {
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compatible = "qcom,pshold";
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reg = <0xc264000 0x4>,
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<0x1fd3000 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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dcc: dcc_v2@117f000 {
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compatible = "qcom,dcc-v2";
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reg = <0x117f000 0x1000>,
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<0x1100000 0x2000>;
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qcom,transaction_timeout = <0>;
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reg-names = "dcc-base", "dcc-ram-base";
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dcc-ram-offset = <0x800>;
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};
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watchdog: qcom,wdt@17817000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17817000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <1 3 0>, <1 2 0>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <10000>;
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qcom,wakeup-enable;
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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qcom,mpm2-sleep-counter@c221000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0xc221000 0x1000>;
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clock-frequency = <32768>;
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};
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mem_dump {
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compatible = "qcom,mem-dump";
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memory-region = <&dump_mem>;
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rpmh {
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qcom,dump-size = <0x200000>;
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qcom,dump-id = <0xec>;
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};
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rpm_sw {
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qcom,dump-size = <0x28000>;
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qcom,dump-id = <0xea>;
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};
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pmic {
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qcom,dump-size = <0x80000>;
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qcom,dump-id = <0xe4>;
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};
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tmc_etf {
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qcom,dump-size = <0x4000>;
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qcom,dump-id = <0xf1>;
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};
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etr_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x100>;
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};
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etf_reg {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0x102>;
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};
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misc_data {
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qcom,dump-size = <0x1000>;
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qcom,dump-id = <0xe8>;
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};
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};
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qcom,msm-imem@1468f000 {
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compatible = "qcom,msm-imem";
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reg = <0x1468f000 0x1000>; /* Address and size of IMEM */
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ranges = <0x0 0x1468f000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie_pipe_clk: pcie-0-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_pipe_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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bi_tcxo: bi_tcxo {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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bi_tcxo_ao: bi_tcxo_ao {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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aopcc: clock-controller@0 {
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compatible = "qcom,aop-qmp-clk";
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mboxes = <&qmp_aop 0>;
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mbox-names = "qdss_clk";
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#clock-cells = <1>;
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};
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rpmhcc: clock-controller@1 {
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compatible = "qcom,dummycc";
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clock-output-names = "rpmhcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gcc: clock-controller@100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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serial_uart: serial@831000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x831000 0x200>;
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interrupts = <0 26 0>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart3_console_active>;
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pinctrl-1 = <&uart3_console_sleep>;
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status = "ok";
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};
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apsscc: clock-controller@17808000 {
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compatible = "qcom,dummycc";
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clock-output-names = "apsscc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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apps_rsc: rsc@17830000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17830000 0x10000>,
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<0x17840000 0x10000>;
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reg-names = "drv-0", "drv-1";
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <1>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<CONTROL_TCS 1>;
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apps_bcm_voter: bcm_voter {
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compatible = "qcom,bcm-voter";
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};
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system_pm {
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compatible = "qcom,system-pm";
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};
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};
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pdc: interrupt-controller@b210000 {
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compatible = "qcom,sdxlemur-pdc";
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reg = <0xb210000 0x10000>;
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qcom,pdc-ranges = <0 147 52>, <52 266 32>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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/* GCC GDSCs */
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gcc_pcie_gdsc: qcom,gdsc@143004 {
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compatible = "regulator-fixed";
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reg = <0x143004 0x4>;
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regulator-name = "gcc_pcie_gdsc";
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};
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gcc_usb30_gdsc: qcom,gdsc@117004 {
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compatible = "regulator-fixed";
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reg = <0x117004 0x4>;
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regulator-name = "gcc_usb30_gdsc";
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};
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system_noc: interconnect@1620000 {
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compatible = "qcom,sdxlemur-system_noc";
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reg = <0x1620000 0x31200>;
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mem_noc: interconnect@9680000 {
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compatible = "qcom,sdxlemur-mem_noc";
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reg = <0x9680000 0x27200>;
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mc_virt: interconnect {
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compatible = "qcom,sdxlemur-mc_virt";
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#interconnect-cells = <1>;
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qcom,bcm-voter-names = "hlos";
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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tcsr_mutex_block: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x1f40000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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cache-controller@9200000 {
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compatible = "qcom,sdxlemur-llcc", "qcom,llcc-v2";
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reg = <0x9200000 0x50000>;
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reg-names = "llcc_base";
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cap-based-alloc-and-pwr-collapse;
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clocks = <&aopcc QDSS_CLK>;
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clock-names = "aopcc_closks";
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};
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smem: qcom,smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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apcs_glb: mailbox@0x17811000 {
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compatible = "qcom,sdxlemur-apcs-gcc";
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reg = <0x17811000 0xb9>;
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#mbox-cells = <1>;
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};
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qcom,smp2p-modem@1799000c {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs_glb 14>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
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qcom,entry-name = "ipa";
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#qcom,smem-state-cells = <1>;
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};
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/* ipa - inbound entry from mss */
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smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&apcs_glb 15>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-data5-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA5_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl0";
|
|
};
|
|
|
|
qcom,glinkpkt-data6-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA6_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl1";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-data21 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA21";
|
|
qcom,glinkpkt-dev-name = "smd21";
|
|
};
|
|
|
|
qcom,glinkpkt-data22 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA22";
|
|
qcom,glinkpkt-dev-name = "smd22";
|
|
};
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
reg = <0xc310000 0x1000>;
|
|
reg-names = "msgram";
|
|
mboxes = <&apcs_glb 0>;
|
|
interrupts = <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "aop";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aop-msg-client {
|
|
compatible = "qcom,debugfs-qmp-client";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0xd00>,
|
|
<0xc600000 0x2000000>,
|
|
<0xe600000 0x100000>,
|
|
<0xe700000 0xa0000>,
|
|
<0xc40a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
};
|
|
};
|
|
|
|
#include "sdxlemur-pinctrl.dtsi"
|
|
#include "sdxlemur-stub-regulator.dtsi"
|
|
#include "msm-arm-smmu-sdxlemur.dtsi"
|
|
#include "sdxlemur-ion.dtsi"
|
|
#include "sdxlemur-usb.dtsi"
|
|
#include "sdxlemur-pm.dtsi"
|
|
#include "sdxlemur-pcie.dtsi"
|