mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
4b471a8075
Update the timeout and add flag to skip status check on disable for PCIE GDSC's. Change-Id: I560d9ba9986bb90ba07bf600464b44e4a580d0bd
224 lines
5.4 KiB
Plaintext
224 lines
5.4 KiB
Plaintext
&soc {
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/* GDSCs in GCC */
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gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,gdsc";
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reg = <0x16b004 0x4>;
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regulator-name = "gcc_pcie_0_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
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compatible = "qcom,gdsc";
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reg = <0x18d004 0x4>;
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regulator-name = "gcc_pcie_1_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,gdsc";
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reg = <0x177004 0x4>;
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regulator-name = "gcc_ufs_phy_gdsc";
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status = "disabled";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@10f004 {
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compatible = "qcom,gdsc";
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reg = <0x10f004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {
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compatible = "qcom,gdsc";
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reg = <0x17d05c 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
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compatible = "qcom,gdsc";
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reg = <0x17d050 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
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compatible = "qcom,gdsc";
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reg = <0x17d058 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_mdp0_gdsc: qcom,gdsc@17d078 {
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compatible = "qcom,gdsc";
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reg = <0x17d078 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_mdp0_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_mdp1_gdsc: qcom,gdsc@17d07c {
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compatible = "qcom,gdsc";
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reg = <0x17d07c 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_mdp1_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
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compatible = "qcom,gdsc";
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reg = <0x17d054 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
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compatible = "qcom,gdsc";
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reg = <0x17d06c 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {
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compatible = "qcom,gdsc";
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reg = <0x17d060 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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qcom,gds-timeout = <500>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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/* GDSCs in CAMCC */
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cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 {
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compatible = "qcom,gdsc";
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reg = <0xad0c120 0x4>;
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regulator-name = "cam_cc_titan_top_gdsc";
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status = "disabled";
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};
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cam_cc_bps_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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reg = <0xad07004 0x4>;
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regulator-name = "cam_cc_bps_gdsc";
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status = "disabled";
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};
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cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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reg = <0xad0a004 0x4>;
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regulator-name = "cam_cc_ife_0_gdsc";
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status = "disabled";
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};
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cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 {
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compatible = "qcom,gdsc";
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reg = <0xad0b004 0x4>;
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regulator-name = "cam_cc_ife_1_gdsc";
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status = "disabled";
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};
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cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 {
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compatible = "qcom,gdsc";
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reg = <0xad0b070 0x4>;
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regulator-name = "cam_cc_ife_2_gdsc";
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status = "disabled";
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};
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cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 {
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compatible = "qcom,gdsc";
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reg = <0xad08004 0x4>;
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regulator-name = "cam_cc_ipe_0_gdsc";
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status = "disabled";
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};
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/* GDSCs in DISPCC */
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disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "qcom,gdsc";
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reg = <0xaf03000 0x4>;
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regulator-name = "disp_cc_mdss_core_gdsc";
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proxy-supply = <&disp_cc_mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GDSCs in GPUCC */
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gpu_gx_domain_addr: syscon@3d9158c {
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compatible = "syscon";
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reg = <0x3d9158c 0x4>;
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};
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gpu_cx_hw_ctrl: syscon@3d91540 {
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compatible = "syscon";
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reg = <0x3d91540 0x4>;
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};
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gpu_gx_sw_reset: syscon@3d91008 {
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compatible = "syscon";
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reg = <0x3d91008 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@3d9106c {
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compatible = "qcom,gdsc";
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reg = <0x3d9106c 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@3d9100c {
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compatible = "qcom,gdsc";
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reg = <0x3d9100c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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sw-reset = <&gpu_gx_sw_reset>;
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domain-addr = <&gpu_gx_domain_addr>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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/* GDSCs in VIDEOCC */
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video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 {
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compatible = "qcom,gdsc";
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reg = <0xabf0d18 0x4>;
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regulator-name = "video_cc_mvs0_gdsc";
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status = "disabled";
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};
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video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 {
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compatible = "qcom,gdsc";
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reg = <0xabf0bf8 0x4>;
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regulator-name = "video_cc_mvs0c_gdsc";
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status = "disabled";
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};
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video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 {
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compatible = "qcom,gdsc";
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reg = <0xabf0d98 0x4>;
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regulator-name = "video_cc_mvs1_gdsc";
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status = "disabled";
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};
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video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 {
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compatible = "qcom,gdsc";
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reg = <0xabf0c98 0x4>;
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regulator-name = "video_cc_mvs1c_gdsc";
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status = "disabled";
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};
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};
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