mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 20:28:49 +00:00
b0e5152a74
Add devicetree bindings snapshot to the devicetree project.
This snapshot is taken as of the
'commit 5fba1b18cfc72e264e5f3ce49020ed322aa6ac9f ("Merge 5.6-rc3
into android-mainline")' of the kernel project.
Change-Id: Ia087ab2b7d4a2616ea446a69683a8b5b821d0448
61 lines
1.5 KiB
Plaintext
61 lines
1.5 KiB
Plaintext
High-Frequency PLL (HFPLL)
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PROPERTIES
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- compatible:
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Usage: required
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Value type: <string>:
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shall contain only one of the following. The generic
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compatible "qcom,hfpll" should be also included.
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"qcom,hfpll-ipq8064", "qcom,hfpll"
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"qcom,hfpll-apq8064", "qcom,hfpll"
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"qcom,hfpll-msm8974", "qcom,hfpll"
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"qcom,hfpll-msm8960", "qcom,hfpll"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: address and size of HPLL registers. An optional second
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element specifies the address and size of the alias
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register region.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: reference to the xo clock.
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- clock-names:
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Usage: required
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Value type: <stringlist>
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Definition: must be "xo".
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- clock-output-names:
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Usage: required
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Value type: <string>
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Definition: Name of the PLL. Typically hfpllX where X is a CPU number
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starting at 0. Otherwise hfpll_Y where Y is more specific
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such as "l2".
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Example:
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1) An HFPLL for the L2 cache.
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clock-controller@f9016000 {
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compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
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reg = <0xf9016000 0x30>;
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clocks = <&xo_board>;
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clock-names = "xo";
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clock-output-names = "hfpll_l2";
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};
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2) An HFPLL for CPU0. This HFPLL has the alias register region.
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clock-controller@f908a000 {
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compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
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reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
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clocks = <&xo_board>;
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clock-names = "xo";
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clock-output-names = "hfpll0";
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};
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