mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 14:44:08 +00:00
f6ab82f0cd
Enable 788MHz GPU FMAX speed bin for anorak as per latest requirement. Change-Id: Idc7ff144a74d9f27e309978df2d955851bc47522
741 lines
16 KiB
Plaintext
741 lines
16 KiB
Plaintext
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#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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msm_gpu: qcom,kgsl-3d0@3d00000 {
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compatible = "qcom,adreno-gpu-gen7-6-0", "qcom,kgsl-3d0";
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status = "ok";
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reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
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<0x03d50000 0x10000>, <0x03d9e000 0x1000>,
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<0x10900000 0x80000>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
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"cx_misc", "qdss_gfx";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 286 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq", "freq_limiter_irq";
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resets = <&gpucc GPUCC_GPU_CC_FREQUENCY_LIMITER_IRQ_CLEAR>;
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reset-names = "freq_limiter_irq_clear";
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/*
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* HLOS1_VOTE_GPU_SMMU_CLK enables GPU_CC_MEMNOC_GFX_CLK and
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* GCC_GPU_MEMNOC_GFX_CLK.
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*/
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clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_HUB_CX_INT_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&aoss_qmp>;
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clock-names = "gpu_cc_hlos1_vote_gpu_smmu",
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"gpu_cc_ahb",
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"gpu_cc_cx_gmu",
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"gpu_cc_hub_cx_int",
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"gcc_gpu_snoc_dvm_gfx",
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"apb_pclk";
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qcom,gpu-model = "Adreno740v3";
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qcom,chipid = <0x43050b00>;
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qcom,no-nap;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <4>;
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
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qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
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"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
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interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-cnoc =
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<0>, /* Off */
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<100>; /* On */
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qcom,bus-table-ddr =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(451, 4)>, /* index=1 */
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<MHZ_TO_KBPS(547, 4)>, /* index=2 */
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<MHZ_TO_KBPS(681, 4)>, /* index=3 */
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<MHZ_TO_KBPS(768, 4)>, /* index=4 */
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<MHZ_TO_KBPS(1555, 4)>, /* index=5 */
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<MHZ_TO_KBPS(1708, 4)>, /* index=6 */
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<MHZ_TO_KBPS(2092, 4)>, /* index=7 */
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<MHZ_TO_KBPS(2736, 4)>, /* index=8 */
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<MHZ_TO_KBPS(3867, 4)>; /* index=9 */
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nvmem-cells = <&gpu_speed_bin>;
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nvmem-cell-names = "speed_bin";
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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/* Power levels */
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <9>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <690000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <9>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <640000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <599000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <545000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <492000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <456000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <421000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <350000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <4>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xc0295ffd>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <317000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <2>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc0295ffd>;
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};
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <285000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xe02a5ffd>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <146>;
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qcom,initial-pwrlevel = <9>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <690000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <9>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <640000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <599000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <545000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <492000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <456000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <421000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <350000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <4>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xc0295ffd>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <317000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <2>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc0295ffd>;
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};
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <285000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xe02a5ffd>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <167>;
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qcom,initial-pwrlevel = <12>;
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <788000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <9>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882c5ffd>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <750000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <9>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <730000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <690000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xa82c5ffd>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <640000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <599000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <545000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <492000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <456000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <421000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <5>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0x882e5ffd>;
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};
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qcom,gpu-pwrlevel@10 {
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reg = <10>;
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qcom,gpu-freq = <350000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <4>;
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qcom,bus-max = <9>;
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qcom,acd-level = <0xc0295ffd>;
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};
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qcom,gpu-pwrlevel@11 {
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reg = <11>;
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qcom,gpu-freq = <317000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <2>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc0295ffd>;
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};
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qcom,gpu-pwrlevel@12 {
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reg = <12>;
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qcom,gpu-freq = <285000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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|
|
|
qcom,acd-level = <0xe02a5ffd>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,speed-bin = <168>;
|
|
qcom,initial-pwrlevel = <9>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
reg = <0>;
|
|
qcom,gpu-freq = <690000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <9>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0xa82c5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
reg = <1>;
|
|
qcom,gpu-freq = <640000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
|
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0x882e5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
reg = <2>;
|
|
qcom,gpu-freq = <599000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0x882e5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
reg = <3>;
|
|
qcom,gpu-freq = <545000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
|
|
|
qcom,bus-freq = <9>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0x882e5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <492000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0x882e5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <5>;
|
|
qcom,gpu-freq = <456000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
|
|
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0x882e5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
reg = <6>;
|
|
qcom,gpu-freq = <421000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
|
|
|
qcom,bus-freq = <8>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0x882e5ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
reg = <7>;
|
|
qcom,gpu-freq = <350000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
|
|
qcom,bus-freq = <7>;
|
|
qcom,bus-min = <4>;
|
|
qcom,bus-max = <9>;
|
|
|
|
qcom,acd-level = <0xc0295ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
reg = <8>;
|
|
qcom,gpu-freq = <317000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
|
|
|
qcom,bus-freq = <5>;
|
|
qcom,bus-min = <2>;
|
|
qcom,bus-max = <5>;
|
|
|
|
qcom,acd-level = <0xc0295ffd>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@9 {
|
|
reg = <9>;
|
|
qcom,gpu-freq = <285000000>;
|
|
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
|
|
|
qcom,bus-freq = <1>;
|
|
qcom,bus-min = <1>;
|
|
qcom,bus-max = <5>;
|
|
|
|
qcom,acd-level = <0xe02a5ffd>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,gpu-mempools {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "qcom,gpu-mempools";
|
|
|
|
/* 4K Page Pool configuration */
|
|
qcom,gpu-mempool@0 {
|
|
reg = <0>;
|
|
qcom,mempool-page-size = <4096>;
|
|
qcom,mempool-reserved = <2048>;
|
|
};
|
|
/* 8K Page Pool configuration */
|
|
qcom,gpu-mempool@1 {
|
|
reg = <1>;
|
|
qcom,mempool-page-size = <8192>;
|
|
qcom,mempool-reserved = <1024>;
|
|
};
|
|
/* 64K Page Pool configuration */
|
|
qcom,gpu-mempool@2 {
|
|
reg = <2>;
|
|
qcom,mempool-page-size = <65536>;
|
|
qcom,mempool-reserved = <256>;
|
|
};
|
|
/* 128K Page Pool configuration */
|
|
qcom,gpu-mempool@3 {
|
|
reg = <3>;
|
|
qcom,mempool-page-size = <131072>;
|
|
qcom,mempool-reserved = <128>;
|
|
};
|
|
/* 256K Page Pool configuration */
|
|
qcom,gpu-mempool@4 {
|
|
reg = <4>;
|
|
qcom,mempool-page-size = <262144>;
|
|
qcom,mempool-reserved = <80>;
|
|
};
|
|
/* 1M Page Pool configuration */
|
|
qcom,gpu-mempool@5 {
|
|
reg = <5>;
|
|
qcom,mempool-page-size = <1048576>;
|
|
qcom,mempool-reserved = <32>;
|
|
};
|
|
};
|
|
};
|
|
|
|
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
reg = <0x03da0000 0x40000>;
|
|
|
|
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
|
|
|
gfx3d_user: gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <&kgsl_smmu 0x0 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
|
|
gfx3d_lpac: gfx3d_lpac {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <&kgsl_smmu 0x1 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
|
|
gfx3d_secure: gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <&kgsl_smmu 0x2 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
};
|
|
|
|
gmu: qcom,gmu@3d69000 {
|
|
compatible = "qcom,gen7-gmu";
|
|
|
|
reg = <0x3d68000 0x37000>,
|
|
<0xb290000 0x10000>,
|
|
<0x03D40000 0x10000>;
|
|
|
|
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
|
|
|
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hfi", "gmu";
|
|
|
|
regulator-names = "vddcx", "vdd";
|
|
|
|
vddcx-supply = <&gpu_cc_cx_gdsc>;
|
|
vdd-supply = <&gpu_cc_gx_gdsc>;
|
|
|
|
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_CXO_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&aoss_qmp>;
|
|
|
|
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
|
"smmu_vote", "ahb_clk", "hub_clk", "apb_pclk";
|
|
|
|
qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
|
<550000000 RPMH_REGULATOR_LEVEL_SVS>;
|
|
|
|
iommus = <&kgsl_smmu 0x5 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
};
|