mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 14:44:08 +00:00
337 lines
7.6 KiB
Plaintext
337 lines
7.6 KiB
Plaintext
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a615_zap";
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memory-region = <&pil_gpu_micro_code_mem>;
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};
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msm_gpu: qcom,kgsl-3d0@5900000 {
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compatible = "qcom,kgsl-3d0", "qcom,adreno-gpu-a619-holi";
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status = "ok";
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reg = <0x5900000 0x40000>,
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<0x5961000 0x800>,
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<0x0596A000 0x30000>,
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<0x599E000 0x1000>;
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reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "gmu_wrapper", "cx_misc";
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interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_BIMC_GPU_AXI_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>;
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clock-names = "core_clk", "rbbmtimer_clk", "iface_clk",
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"ahb_clk", "mem_clk", "gmu_clk";
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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qcom,chipid = <0x06010900>;
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nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
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nvmem-cell-names = "speed_bin", "gaming_bin";
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qcom,initial-pwrlevel = <4>;
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qcom,gpu-quirk-secvid-set-once;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <2>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI>;
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interconnect-names = "gpu_icc_path";
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qcom,bus-table-ddr7 =
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<MHZ_TO_KBPS(0, 4)>, /* index=0 */
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<MHZ_TO_KBPS(451, 4)>, /* index=1 (LOW SVS) */
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<MHZ_TO_KBPS(547, 4)>, /* index=2(LOW SVS) */
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<MHZ_TO_KBPS(681, 4)>, /* index=3 (SVS) */
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<MHZ_TO_KBPS(768, 4)>, /* index=4 (SVS) */
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<MHZ_TO_KBPS(1017, 4)>, /* index=5 (SVS) */
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<MHZ_TO_KBPS(1353, 4)>, /* index=6 (NOM) */
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<MHZ_TO_KBPS(1555, 4)>, /* index=7 (NOM) */
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<MHZ_TO_KBPS(1804, 4)>, /* index=8 (TURBO) */
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<MHZ_TO_KBPS(2092, 4)>; /* index=9 (TURBO_L1) */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/*
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* Speed-bin zero is default speed bin.
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* For rest of the speed bins, speed-bin value
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* is calulated as FMAX/4.8 MHz (round up to zero
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* decimal places) + 2.
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*/
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,ca-target-pwrlevel = <5>;
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qcom,initial-pwrlevel = <6>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <875000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <9>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <800000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <565000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <8>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <138>;
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qcom,ca-target-pwrlevel = <3>;
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qcom,initial-pwrlevel = <4>;
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/* NOM_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <650000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <7>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <9>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <565000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <5>;
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qcom,bus-max-ddr7 = <8>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <92>;
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qcom,ca-target-pwrlevel = <2>;
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qcom,initial-pwrlevel = <1>;
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/* SVS_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <430000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <5>;
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qcom,bus-min-ddr7 = <4>;
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qcom,bus-max-ddr7 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <355000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <4>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7= <5>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <253000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <4>;
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};
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};
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};
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};
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kgsl_msm_iommu: qcom,kgsl-iommu@5940000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x5940000 0x10000>;
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vddcx-supply = <&gpu_cx_gdsc>;
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clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gcc_bimc_gpu_axi", "gpu_cc_ahb",
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"gcc_gpu_memnoc_gfx";
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x0>;
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qcom,iommu-dma = "disabled";
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0x2>;
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qcom,iommu-dma = "disabled";
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};
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};
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};
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