mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
16a1986acf
Disable eMMC for shima so that the bus speed mode changes can be made in the main shima.dtsi file without breaking the shima RUMI as eMMC is not needed for shima RUMI. Change-Id: Ie94f812a025547981b1b31ae745f8ed292bcc660
187 lines
3.3 KiB
Plaintext
187 lines
3.3 KiB
Plaintext
#include <dt-bindings/clock/qcom,gcc-shima.h>
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#include <dt-bindings/gpio/gpio.h>
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&soc {
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timer {
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clock-frequency = <5000000>;
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};
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timer@17c20000 {
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clock-frequency = <5000000>;
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};
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wdog: qcom,wdt@17c10000 {
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status = "disabled";
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};
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usb_emu_phy_0: usb_emu_phy@a720000 {
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compatible = "qcom,usb-emu-phy";
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reg = <0x0a720000 0x9500>;
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qcom,emu-init-seq = <0xffff 0x4
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0xfff0 0x4
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0x100000 0x20
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0x0 0x20
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0x101f0 0x20
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0x100000 0x3c
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0x0 0x3c
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0x10060 0x3c
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0x0 0x4>;
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};
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bi_tcxo: bi_tcxo {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <2>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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bi_tcxo_ao: bi_tcxo_ao {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <2>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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};
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&usb2_phy0 {
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status = "disabled";
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};
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&usb_qmp_dp_phy {
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status = "disabled";
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};
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&usb0 {
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/delete-property/ extcon;
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dwc3@a600000 {
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usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
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maximum-speed = "high-speed";
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dr_mode = "peripheral";
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};
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};
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&rpmhcc {
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compatible = "qcom,dummycc";
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clock-output-names = "rpmhcc_clocks";
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qrbtc-sdm845";
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vdda-phy-supply = <&L10C>;
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vdda-pll-supply = <&L6B>;
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vdda-phy-max-microamp = <97100>;
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vdda-pll-max-microamp = <18400>;
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status = "ok";
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};
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&ufshc_mem {
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limit-tx-hs-gear = <1>;
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limit-rx-hs-gear = <1>;
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&L7B>;
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vcc-max-microamp = <800000>;
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vccq-supply = <&L9B>;
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vccq-max-microamp = <900000>;
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vccq2-supply = <&S10B>;
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vccq2-max-microamp = <800000>;
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qcom,vddp-ref-clk-supply = <&L9B>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,disable-lpm;
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rpm-level = <0>;
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spm-level = <0>;
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status = "ok";
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};
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&sdhc_1 {
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status = "disabled";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_on>;
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pinctrl-1 = <&sdc1_off>;
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vdd-supply = <&pm8350_l7>;
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qcom,vdd-voltage-level = <2960000 2960000>;
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qcom,vdd-current-level = <0 570000>;
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vdd-io-supply = <&pm8350_s10>;
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qcom,vdd-io-always-on;
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qcom,vdd-io-lpm-sup;
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qcom,vdd-io-voltage-level = <1800000 1800000>;
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qcom,vdd-io-current-level = <0 325000>;
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cap-mmc-highspeed;
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};
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&sdhc_2 {
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status = "ok";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc2_on>;
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pinctrl-1 = <&sdc2_off>;
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vdd-supply = <&pm8350c_l9>;
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qcom,vdd-voltage-level = <2960000 2960000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&pm8350c_l6>;
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qcom,vdd-io-voltage-level = <2960000 2960000>;
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qcom,vdd-io-current-level = <0 22000>;
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cap-sd-highspeed;
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cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
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};
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/* Debug UART console */
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&qupv3_se13_2uart {
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qcom,rumi_platform;
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};
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&gcc {
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clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;
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};
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&aopcc {
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compatible = "qcom,dummycc";
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clock-output-names = "qdss_clocks";
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};
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&cpufreq_hw {
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clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
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};
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&camcc {
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clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>;
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};
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&debugcc {
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clocks = <&bi_tcxo>;
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};
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&videocc {
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clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>;
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};
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&gpucc {
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clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
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};
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&dispcc {
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clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
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};
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