mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 14:44:08 +00:00
0d09b83b21
Add below 2 DT properties to switch ufs irq affinity dynamically *qcom,prime-mask. *qcom,silver-mask. Change-Id: I99b02a2e63b024e553d268756d6a2d4df1e99a31
307 lines
5.8 KiB
Plaintext
307 lines
5.8 KiB
Plaintext
#include "cape.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Ukee SoC";
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compatible = "qcom,ukee";
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qcom,msm-id = <591 0x10000>;
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};
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&msm_gpu {
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qcom,initial-pwrlevel = <5>;
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/delete-property/qcom,gpu-model;
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qcom,gpu-model = "Adreno725v1";
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nvmem-cells = <&gpu_speed_bin>;
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nvmem-cell-names = "speed_bin";
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/delete-node/qcom,gpu-pwrlevels;
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/* Power levels */
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <580000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <7>;
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qcom,bus-max = <11>;
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qcom,acd-level = <0x882e5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <515000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <6>;
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qcom,bus-max = <8>;
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qcom,acd-level = <0x882e5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <439000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <3>;
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qcom,bus-max = <8>;
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qcom,acd-level = <0xc0285ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <364000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <6>;
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qcom,acd-level = <0xc0285ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <324000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <2>;
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qcom,bus-min = <1>;
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qcom,bus-max = <6>;
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qcom,acd-level = <0xc02a5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <285000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <2>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc02c5ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <220000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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qcom,bus-freq = <2>;
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qcom,bus-min = <1>;
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qcom,bus-max = <5>;
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qcom,acd-level = <0xc8285ffd>;
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qcom,cx-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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};
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&gcc_pcie_1_gdsc {
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status = "disabled";
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};
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&clock_gcc {
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protected-clocks = <GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
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<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_CLKREF_EN>,
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<GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_AUX_CLK>,
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<GCC_PCIE_1_PHY_AUX_CLK_SRC>, <GCC_PCIE_1_PHY_RCHNG_CLK>,
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<GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, <GCC_PCIE_1_PIPE_CLK>,
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<GCC_PCIE_1_PIPE_CLK_SRC>, <GCC_PCIE_1_SLV_AXI_CLK>,
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<GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
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};
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&qcom_memlat {
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ddr {
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silver {
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qcom,cpufreq-memfreq-tbl =
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< 1132800 547000 >,
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< 1440000 768000 >,
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< 1670400 1555000 >;
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};
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gold {
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qcom,cpufreq-memfreq-tbl =
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< 883200 547000 >,
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< 1113600 768000 >,
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< 1324800 1555000 >,
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< 1881600 2092000 >,
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< 2227200 2736000 >,
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< 2400000 3196000 >;
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};
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prime {
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qcom,cpufreq-memfreq-tbl =
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< 787200 547000 >,
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< 1036800 768000 >,
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< 1286400 1555000 >,
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< 1881600 2092000 >,
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< 2131200 2736000 >,
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< 2400000 3196000 >;
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};
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gold-compute {
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qcom,cpufreq-memfreq-tbl =
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< 1881600 547000 >,
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< 2400000 1555000 >;
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};
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prime-latfloor {
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qcom,cpufreq-memfreq-tbl =
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< 2131200 547000 >,
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< 2400000 3196000 >;
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};
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};
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llcc {
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silver {
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qcom,cpufreq-memfreq-tbl =
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< 556800 300000 >,
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< 1440000 466000 >,
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< 1804800 600000 >;
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};
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gold {
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qcom,cpufreq-memfreq-tbl =
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< 633600 300000 >,
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< 1113600 466000 >,
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< 1324800 600000 >,
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< 1881600 806000 >,
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< 2227200 933000 >,
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< 2400000 1066000 >;
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};
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gold-compute {
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qcom,cpufreq-memfreq-tbl =
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< 1881600 300000 >,
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< 2400000 600000 >;
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};
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};
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l3 {
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silver {
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qcom,cpufreq-memfreq-tbl =
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< 300000 300000 >,
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< 441600 403200 >,
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< 556800 518400 >,
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< 691200 710400 >,
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< 806400 806400 >,
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< 940800 902400 >,
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< 1056000 998400 >,
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< 1132800 1075200 >,
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< 1324800 1267200 >,
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< 1440000 1478400 >,
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< 1670400 1593600 >,
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< 1804800 1708800 >;
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};
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gold {
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qcom,cpufreq-memfreq-tbl =
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< 633600 518400 >,
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< 883200 614400 >,
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< 1113600 902400 >,
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< 1324800 998400 >,
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< 1651200 1267200 >,
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< 1996800 1478400 >,
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< 2227200 1593600 >,
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< 2400000 1708800 >;
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};
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prime {
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qcom,cpufreq-memfreq-tbl =
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< 787200 518400 >,
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< 921600 614400 >,
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< 1171200 902400 >,
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< 1401600 998400 >,
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< 1651200 1267200 >,
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< 1996800 1478400 >,
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< 2131200 1593600 >,
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< 2400000 1708800 >;
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};
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prime-compute {
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qcom,cpufreq-memfreq-tbl =
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< 1996800 300000 >,
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< 2400000 1708800 >;
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};
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};
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ddrqos {
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gold {
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qcom,cpufreq-memfreq-tbl =
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< 1881600 0 >,
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< 2400000 1 >;
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};
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prime-latfloor {
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qcom,cpufreq-memfreq-tbl =
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< 1996800 0 >,
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< 2400000 1 >;
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};
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};
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};
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&soc {
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remoteproc-spss@1880000 {
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status = "disabled";
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};
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cache-controller@19200000 {
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compatible = "qcom,ukee-llcc", "qcom,llcc-v21";
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};
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ssc_sensors: qcom,msm-ssc-sensors {
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compatible = "qcom,msm-ssc-sensors";
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status = "ok";
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qcom,firmware-name = "slpi2.mdt";
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qcom,rproc-handle = <&slpi_pas>;
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};
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qfprom: qfprom@221c8000 {
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compatible = "qcom,qfprom";
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reg = <0x221c8000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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read-only;
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ranges;
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gpu_speed_bin: gpu_speed_bin@119 {
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reg = <0x119 0x2>;
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bits = <5 8>;
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};
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};
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qfprom_sys: qfprom@0 {
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compatible = "qcom,qfprom-sys";
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};
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};
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&ufshc_mem
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{
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qcom,prime-mask = <0x70>;
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qcom,silver-mask = <0x0f>;
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};
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